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We are tasked with creating a 4 to 1 multiplexer with 4-bit inputs. I believe I fully understand how to create a 4 to 1 1-bit multiplexer, but I completely do not understand what the 'input' side and 'output' side of a multi-bit (4-bit in this case) 4 to 1 multiplexer would look like. This is my first ever introduction to circuits so I do not understand more advanced topics.

My updated attempts at what the MUX and DMX would look like are below: MUX

DMX

Diagrams were made in Logisim.

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  • \$\begingroup\$ This is a concept I do not understand, which is part of a much larger assignment that requires us to create the following telephony circuit(for reference): !postimg.org/image/vzk704eob And this is the specific part I am working on creating right now, and what this question pertains to: !postimg.org/image/t1q0p7h2t \$\endgroup\$ – SeesSound Oct 1 '16 at 22:21
  • \$\begingroup\$ Your second image looks reasonable at first glance for a parallel 16to4 MUX but your question seems to want serial shifting of the data (typical in a communications context) with a out of band clocking signal. \$\endgroup\$ – KalleMP Oct 1 '16 at 23:22
  • \$\begingroup\$ @KalleMP considering just the 'serial shifting of the data' part of your reply. What am I looking to do in terms of drawing the circuit? Would it be a 4 bit shift register, which has a splitter(4 fan out, 1 bit width in) attached to it, and then the splitter extends to one of the inputs of a 4 to 1 single MUX (such that I am only dealing with 1 MUX and not 4 now as is in the diagram in the OP)? What does this mean for the data travelling through the '1 bit width in' of the splitter. Am I not requiring 4 bits into the MUX and just require 4, 1 bits? Thanks! \$\endgroup\$ – SeesSound Oct 2 '16 at 0:00
  • \$\begingroup\$ I guess the assignment is about indicating how time slicing is managed in simple high speed networks. These days most things work with larger packets than 4 bits and will handle more than 4 parallel streams. The idea is that you mux in 4 bits from the 4 sources (one from each) into the shift register and then shift them out a bit at a time. Resynchronising would be an added complexity that has been kind of ignored here. \$\endgroup\$ – KalleMP Oct 3 '16 at 19:37
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One of the main properties that your circuit design must have is Modularity that is you build a single module and then combine this module with other modules to build a bigger module, this help making your design easier.

Now back to your problem; In the first picture you provided the implementation of a 4:1 multiplexer

enter image description here

which could be described by this black box

enter image description here

Now the behavioral description of this black box is

if(s0s1==00)
 output=d0
else if(s0s1==01)
 output=d1
else if(s0s1==10)
 output=d2
else if(s0s1==11)
 output=d3

Now in order to create the 4-bit version of this multiplexer which could be descried with this black box

enter image description here

The behavioral description of this black box is

if(s0s1==00)
 output[3..0]=d0[3..0]    //the 4-bit output is equal to the 4-bit input
else if(s0s1==01)
 output[3..0]=d1[3..0] 
else if(s0s1==10)
 output[3..0]=d2[3..0]
else if(s0s1==11)
 output[3..0]=d3[3..0]

This new circuit has 18 inputs [2 for selecting and 4-bit 4 inputs] and 4 outputs

The implementation of the new circuit would be

enter image description here

However in your design

enter image description here

  1. You are using an 8-input mux instead of the implemented 6-input mux ! this is not the same module you already implemented as a 4:1 mux !
  2. You are connecting the select bits of all the multiplexers to another decoder this will always make only one of the select bits 1 and the other select bits are 0 [since they are connected to a decoder] however this violates the behavioral description of our 4:1 mux

So in order to correct your design

  1. remove the decoder
  2. use the already implemented 4:1 mux with the correct number of inputs
  3. connect all the select lines s0 and s1 to the same select lines of your bigger multiplexer
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  • \$\begingroup\$ You're a gem, thanks for taking time in answering the above. Please let me know if there is any issue with my updated answer. I have also created a DMX that uses the MUX's input. Do you see any issue with either of these new pictures. Thanks. \$\endgroup\$ – SeesSound Oct 2 '16 at 23:05
  • \$\begingroup\$ So far no issues, looks like this is implemented correctly \$\endgroup\$ – Elbehery Oct 3 '16 at 15:01
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A 4-input mux has 4 data inputs and 2 address inputs. The address inputs determine which data input connects to the output. A 4-bit, 4-input mux is simply 4 each 4 input muxes in parallel, with the address inputs connected the same to all muxes. So, if you have 4 data channels, (A0,A1,A3,A3), (B0,B1,B2,B3), (C0,C1,C2,C3) and (D0,D1,D2,D3), and address of 0 will produce 4 outputs: A0,B0,C0 and D0.

Drawing the entire unit as a block will have an input side (usually shown on the left). and an output side. The input side will have 18 inputs - 16 data and 2 address. The output side will have 4 data outputs.

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  • \$\begingroup\$ I am confused by what you mean from "A 4-bit, 4-input mux is simply '4 each 4 input' muxes in 'parallel', with the address inputs connected the 'same' to all muxes". This is the circuit I am trying to draw in the end postimg.org/image/vzk704eob . According to this diagram, the MUX is 4-1 and only has 4 data inputs, not 16. \$\endgroup\$ – SeesSound Oct 1 '16 at 22:51
  • \$\begingroup\$ @SajSeesSound - Sigh. Yes. And there are 4 of them. \$\endgroup\$ – WhatRoughBeast Oct 1 '16 at 23:31
  • \$\begingroup\$ yeah I apologize for the redundancy. I do not quite understand your answer. Are you able to draw out what you mean? \$\endgroup\$ – SeesSound Oct 1 '16 at 23:33
  • \$\begingroup\$ @SajSeesSound - Your lower diagram shows 16 inputs, not 4. Each mux has 4 inputs, but there are 4 muxes, and 4 times 4 is 16. Your diagram is correct. \$\endgroup\$ – WhatRoughBeast Oct 2 '16 at 3:53

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