I am creating a homebrew CPU with 74 series TTL chips.
I have a clock signal that goes to multiple registers. I have a particular register that I only want to update when the opcode is a particular value. So the solution seems to be an AND gate between the clock signal and the output of the logic used to decide if the register should update. This seems the only viable solution as the TTL chip does not have a separate enable line for controlling if the clock is used or not.
My concern is timing. Will the extra AND gate delay cause problems because it delays the clock signal to this register compared to other registers? Or should I place a double NOT gate on the clock line that is not going to the AND gate so both paths have the same timing?