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I am attempting to make the following digital telephony circuit by applying Time Division Multiplexing(TDM).

I am having trouble figuring out how to create a 2-bit counter that counts from 0 to 3, adding one at a rising edge of a clock, and then resets the count to zero and so on.

The 2-bit counter will act as the selector line for the MUX, DMX, and the 2-bit decoder.

I am planning on implementing a synchronous J-K Flip-Flop, but it requires two inputs (J and K) in addition to the clock. According to the diagram below, the only input into the counter and that runs the counter is the clock. So how can I implement a J-K without needing the J-K inputs and only needing the clock, or is there a better flip-flop / latch that can be used? Note I am only 2 weeks new to digital circuit design so don't know much..

enter image description here

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  • \$\begingroup\$ Standard async 2 bit counter uses only 1 dual D FF with Qbar1 to D1 input and Q1 to CLK2 and again Qbar2 to D2 with {Q1; Q2) outputs with Q1=/2 , Q2=/4 rising edge clock input 74HC74 to CLK1 \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Oct 3 '16 at 3:35
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There are all sorts of ways.

JK

schematic

simulate this circuit – Schematic created using CircuitLab

T (essentially a JK with both inputs tied together

schematic

simulate this circuit

D (Essentially a JK with the K inverted, and both tied together)

schematic

simulate this circuit

Note that the JK implementation ties the inputs of the first FF high, and this is not shown as an input on most counters.

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  • \$\begingroup\$ what does FF and Logic High represent? \$\endgroup\$ – SeesSound Oct 3 '16 at 3:38
  • \$\begingroup\$ @SajSeesSound - You know how logic deals with 1's and 0's? Well, in most logic systems, a 1 is a high voltage and a 0 is a low. So a logic high is a 1. In CMOS, this is most easily done by connecting to the logic power supply. FF stands for "flip-flop". \$\endgroup\$ – WhatRoughBeast Oct 3 '16 at 3:41
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This is the most common way using a 74HC74

enter image description here

But since not only do you need a 8KHz clock and 2 bit counter , you need a 24 channel counter to decode 1st time slot which is usually done with a CD4020 and gates for /24 for DS1 or use binary addressable 1 of 24 port MUX

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    \$\begingroup\$ That is not a synchronous counter. It is a ripple counter. \$\endgroup\$ – WhatRoughBeast Oct 3 '16 at 12:49
  • \$\begingroup\$ Having designed a DS1 BER test set for 1.544 Mb/s and 8kHz frame rate before. I understand the requirements. Depending how the MUX DEMUX is done it can skew the "Synchronous Counter gate times . All I am saying is this is how it most often done at these slow MUX frequencies. i.e. asynchronously with 8MHz chips operating in this case at much slower rates. Normally the serial link is resync'd with the master bit clock so synchronous counters are complete unnecessary here \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Oct 3 '16 at 15:35

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