Today I ran into a problem with op-amp slew rate when playing with a design where an op-amp spends a lot of time in saturation, only to occasionally "come down" and regulate the output.

(I'm simulating this using LTspice, and the op-amps are somewhat arbitrarily chosen but it should not affect the question.)


I wanted to increase the slew rate to minimize the time it spent from exiting from the saturation and enter the active mode, but when I replaced the slower LT1013 with a model of the TL074, the slew rate of my signal did not increase substantially. Even when the positive and negative inputs of the TL074 were clearly at least 50 mV apart, it did not reach the full speed. This is much more than the maximum input voltage difference. I also checked that it was not limited by the output current, but nothing there.


After a lot of head-scratching I realize that this is because the inputs are not far enough apart. Never having seen this effect before, or at least not thought about it too much, I assumed that as long as the inputs are reasonably different, the operational amplifier will try its best to change the output.

I also remember reading something about this in The Art of Electronics, and when I looked it up, this is pretty much all it has to say about the subject:

5.8.1 Slew rate: general considerations

... A second consequence is best explained with the help of a graph of slew rate versus differential-input signal (Figure 5.12). The point to be made here is that a circuit that demands a substantial slew rate must operate with a substantial voltage error across the op-amp's input terminals.

Slew rates for BJT and JFET

Figure 5.12. A substantial differential-input voltage is required to produce the full op-amp slew rate, as shown in these measured data. For BJT-input op-amps it takes ∼60 mV to reach full slew rate; for JFETs and MOSFETs it's more like a volt.

Bingo. TL074 is a JFET-input op-amp. I adjusted my circuits to get a higher differential voltage, and that solved the immediate problem. A separate simulation gave me results similar to this figure, showing that the models in LTspice are at least reasonably true to reality.

However, the increased differential voltage causes other problems, which I would like to avoid.


... or several related questions. I'm not necessarily looking for answers to each of them, but perhaps more of a general explanation.

  • Does this effect depend on anything else than the JFET/BJT input stage?
  • Are there input stages where an even lower differential input voltage leads to the maximum slew rate? Perhaps some sort of hybrid?
  • Even if there are only two types, do different op-amps of the same type (say, BJT) have different levels?
  • ... if so, is this possible to figure out from the datasheet?

I could not find anything about this on the TL074 datasheet, but that's of course only a single sample.

Somewhat related, is there a common solution, or is this where I would start looking at comparators instead? I might go with a comparator of sorts in the final design, but I still find this problem interesting.

  • \$\begingroup\$ Would it help if you didn't go into saturation but had just enough negative feedback to prevent saturation (without causing anomolous circuit operation due to not quite being in saturation). \$\endgroup\$
    – Andy aka
    Commented Oct 3, 2016 at 20:14
  • \$\begingroup\$ @Andyaka Do you mean something with zener-diodes so the output is limited to some lower voltage? I tried that, and it helped, but it caused some other problems. Eventually I will ask a separate question about that with my actual circuit because I couldn't quite figure out how to connect it. I have to sleep on it a few more days. \$\endgroup\$
    – pipe
    Commented Oct 3, 2016 at 20:19
  • \$\begingroup\$ Yes that's what I mean - i.e. keep it out of sat but in a safe area. \$\endgroup\$
    – Andy aka
    Commented Oct 3, 2016 at 20:39
  • 1
    \$\begingroup\$ What you need to get to serious slew rates, you switch to Comparators (no pun intended) then to ECL comparators with SR= 1600V/us switching 0.8V in 500ps into 50 Ohms like the MAX9691 \$\endgroup\$ Commented Oct 3, 2016 at 21:42
  • 1
    \$\begingroup\$ After an opamp has spent some time in saturation, there will be a thermal offset in its input stage due to one of the transistors carrying all the current. Depending on the opamp, this may wause weird effects and delay settling by a lot longer than you may think. \$\endgroup\$
    – bobflux
    Commented Mar 30, 2017 at 13:01

5 Answers 5


Does this effect depend on anything else than the JFET/BJT input stage?

Slewing can happen in any stage of an OpAmp, it can happen in the input stage, the output stage and any of the intermediary stages. It occurs whenever a capacitor is driven by a fixed current source. For a given configuration one stage sets the limit and determines the slew-rate often this is in fact the input stage.

A typical input stage consists of a differential pair with a tail current source. In equilibrium the current of the tail current source splits equally and when driven hard on transistor takes the whole current. The required voltage to turn one of the transistors (almost) off determines the onset of slewing. It's a fixed voltage for BJTs and a variable voltage for FETs.

If slewing happens in the output stage and the output stage is not symmetrical (e.g. class A) it is possible to have different slew-rates for falling and rising edges.

Are there input stages where an even lower differential input voltage leads to the maximum slew rate? Perhaps some sort of hybrid?

I don't know of any off-the-shelf devices that do this, but certainly there are adaptively biased OpAmps that increase the current through the input stage to improve the slewing behavior.

Even if there are only two types, do different op-amps of the same type (say, BJT) have different levels?

BJTs have a fixed level, unless emitter degeneration is used and FETs can have different levels.

  • \$\begingroup\$ Every answer here gave me good information, but I think this answered my immediate/literal questions, hence the little green check mark. \$\endgroup\$
    – pipe
    Commented Oct 4, 2016 at 20:57

Usually overdriving the input causes longer time to exit from saturation. Note that slew rate is not closely tied to that time, and some op-amps can lollygag around for 50usec or more before deciding to exit from saturation.

I suggest you use an op-amp that is specified for your (ab)use such as the AD8067. That particular one might not be suitable for you (gain must be >= 8 for stability) but the time to exit from saturation is specified and it is reasonable (~200ns) with significant overdrive though.

I don't think I would trust the SPICE models to necessarily model saturation recovery accurately. It could be a lot worse than the simulation would imply, so verify by testing.

  • \$\begingroup\$ "I don't think I would trust the SPICE models to necessarily model saturation recovery accurately.", thank you, I'll definitely keep that in mind. I try not to take the results too seriously, but it's easy to get carried away. \$\endgroup\$
    – pipe
    Commented Oct 4, 2016 at 19:09

I don`t know if the following can help and/or answers some of you questions. Nevertheless,

  • The slew rate is specified and measured with feedback applied (normally, 100% feeedback with a closed-loop gain of unity); in your post, I could not find any mentioning of feedback.

  • Assuming an 1V input step the output will rise to 1V also - however, with a certain delay because the feedback signal does NOT immediately arrive at the inv. input but with a delay of some µseconds.

  • As a consequence, the first stage (diff. amplifier) will be overdriven by the input step and the saturated input transistor(s) are operated as switches.

  • Hence, the compensation capacitor in the second stage is charged with a constant voltage until the feedback signal stops charging because the input stage is brought back to linear operation (equilibrium established by feedback).

  • This charging process results in (and determines) the slewing properties of the amplifier.

  • From the above, we can derive that the input step must be large enough to bring the first stage of the amplifier (without feedback) safely into saturation.


Slew rate is usually limited by the available current drive and output capacitance that the driver sees including internal connections.

How much differential voltage does it take?

Given a slew rate of x V/us and a rise time 0.35/f and a closed loop BW of GBW/Av for a closed loop gain of Av.

Now what is the minimum input signal Vpp to exceed the slew rate specified?

Well that depends on the input frequency and gain, but normally it is well overdriven to determine rated Slew rate and that slew rate is current limited and depends on internal and external load capacitance.


If SR=13V/us typ for C=100pF what is Iout max? enter image description here Ic=1e-10*13e-6 = 1.3 mA

But wait there is no spec for output current.

enter image description here However using 50% Vpp max output swing point to determine the equivalent output resistance , we get 220 Ohms capable of +/7V swing matched to internal losses.

Thus we can only conclude it is NOT output current limited but some internal stages where it is current limited.


Different input diffpairs produce different input linear ranges. And changing to FETs allows other (gate width/length) degrees of freedom. The UA715 uses bipolar emitter degeneration, to achieve fast settling. Here are typical input diffpairs:


simulate this circuit – Schematic created using CircuitLab


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