# Verilog Arithmetic with 8 bits

I am trying to subtract one 8 bit number from another but I keep getting an error that "<=" is unexpected. The rest of it I am just AND-ing the 8th bit of each output. Can someone tell me what is wrong with my code?

module test(n1,n2,n3,z);

input [7:0] n1,n2,n3;

output [7:0] z;

wire [7:0] x1, x2;

x1 <= n1 - n2;

x2 <= n3 - n2;

and and1(z, x1[7],x2[7]);

endmodule


The <= operator can only be used within a procedural block.

A procedural block is begin with the keyword always or initial.

Since you haven't used either of these keywords, you can't use the <= operator.

If you want x1 and x2 to change whenever the inputs change, you should use an assign statement, for example

assign x1 = n1 - n2;


You should use either an assign statement like so:

assign x1 = n1 - n2;


or you can assign with the wire definition like so:

wire [7:0] x1 = n1 - n2;