# How to drive a SPI bus over 5 feet of 26AWG wire?

Below is the circuit I am trying to achieve. The endpoint is a 5V device but my microcontroller (SPI Master) is a 3.3V device so I have to do the voltage translation.

My question is what kind of a circuit should I use to drive the SPI signal over a long wire like that? The circuit I have now (shown below) really distorts the signal badly.

The signal looks quite bad with just the 5 feet wire connected.

• Where is this measurement being taken in your architecture above? Oct 4 '16 at 15:15
• The measurement is taken right at the Connector. I will add this info to the question. Oct 4 '16 at 15:23
• What you are seeing is probably reflections; 1 metre of wire is about 5.3nsec of flight time and the signal edges are faster than that; the difference in reflections at high and low would depend on far end terminations. Oct 4 '16 at 15:30
• Series-terminate the driving end (between translator and connector). Oct 4 '16 at 15:48
• @user1406716 - This question seems related to your older question "Reflection on SPI Clock Signal, termination or stub issue?", which doesn't seem to have been solved (no accepted answer, no update from you in the last 18 days). Unless that earlier question has been solved (or proved to be a measurement artefact), isn't there a risk that your SPI signals have problems, even before adding the 5ft of wire? Oct 4 '16 at 16:41

How about this: you drive a current through the wire, that goes through the LED of an optocoupler on the other side. You drive the LED from the 3V3 supply, and the phototransistor in the opamp from the 5V. This solves two problems: The 3V3 to 5V conversion, and the sensitivity to external noise.

• Not bad, just have to use a high-speed optocoupler. Most are probably not fast enough for this application. Oct 4 '16 at 15:23
• I will add this constraint to the question: the final slave device (an LED strip as shown) - I am buying it off the shelf and cannot add a device at that end. Is there no way around? Oct 4 '16 at 15:23

Add series resistance to the output of the translator to slow down the edge rate. This will reduce the reflection effects and particularly the nasty glitch on the falling edge that threatens to produce rogue clock edges. The resistance needed will depend on a lot of details you haven't shared, so you might have to experiment to find the right value.

This may slow down the edges to the point you have to reduce your data rate. That's just the way it is. If you want high data rates over long distances, you might have to use legitimate transmission lines rather than ad hoc loose wires.

• It's not so much about slowing down the edges as it's matching the line impedance to terminate the reflection. Slowing down the edges is more of a side effect which is actually undesired at higher frequencies. Oct 4 '16 at 16:22
• @Barleyman, If frequency content is kept down, it's entirely reasonable to view a wire as an RLC element, rather than a transmission line. We don't need to pull out transmission line theory to solve every problem. Also it's entirely possible the load has multiple terminations (e.g. multi-drop bus), so even if transmission line analysis and source-series termination gives a nice waveform at the source, it might not give very good results at intermediate points along the line. Oct 4 '16 at 16:30
• Yes, that's what the critical length business in transmission line theory is about ;-) Depending on who you ask, you can ignore impedance if your propagation delay in one direction is <1/4 signal wavelength. In this case about 30MHz. That equals 33ns so your rise time should be more than 16.7ns or double what it is now. Then again some people would think that you should use 1/8th wavelength or less. Oct 4 '16 at 16:41

That would be about 80ns per clock or 12.5MHz SPI bus? And you're driving it over 1.5 meters of a completely unshielded or otherwise balanced 0.4mm diameter wire? Looks like the rise time is about 8ns or 125MHz effective. Ouch.

Theoretically that'd add up to about 200 ohms characteristic impedance so your translator driver should have 180R series resistor to the clock and SDO (MOSI) lines. If you're actually reading data back then you have to add another resistor to the SDI (MISO) line at the far end. If the driver can supply enough current, you can skip the series resistor and add a 200R resistor to the GND at the far end for best effect but this requires 25mA drive which may not be practical.

Depending on how the cable is put together the actual impedance may be (much) less, depending if there is wire right next to it (<<5mm). Experimenting will yield optimal value, start with 47R resistor in series and work your way up in increments of 47R. Alternatively 22R and 22R if you want to fine tune it but it's probably going to be "close enough" with 47R increments.

• How did you work out the characteristic impedance without knowing the spacing between the signal and return wires? Oct 4 '16 at 16:00
• @ThePhoton By presuming the return path is "far" e.g. >10x diameter away. The OP didn't give us any spefics on the cable so this is probably wrong as that would be true for a lone wire only. A little bit of experimentation will yield optimal value which is likely on the ballpark of 33 to 100R. Oct 4 '16 at 16:11