I've got a board with two Altera CPLDs on it with a bit of a programming problem: programming it via JTAG fails.

The JTAG lines run through the first board, through a flex, and a few emerge on the other board underneath some other components. The rest seem to emerge under the CPLDs, which are on top of each other, or back to back for want of a better way of explaining it.

I don't know whether the JTAG lines run parallel all the way, nor do I know what order the tracks are in inside the board - hopefully TDO is away from TCK... The board has at least 4 layers from what I can tell.

When I go to program the device, I can run the "Detect JTAG chain info" utility in MAX+plus II. It returns a message saying "JTAG chain information confirmed by hardware check", which is good. Then, I can run a blank check, which fails.

If I disconnect TDO at the JTAG header and run a piece of wire to the JTAG pins on one of the CPLDs, it works. The data looks mostly fine on the oscilloscope with pretty sharp edges and minimal ringing. However, I get some spurious oscillations at certain points when I probe it:



The traces are as follows:
Yellow: TDO
Cyan: TCK
Magenta: TMS
Green: TDI

You will notice that TCK never quite makes it to the rail occasionally. When it does, it is very sinusoidal and not at all square.

TDO only oscillates when TDI is high, but not every time TDI is high. TCK seems to oscillate when TMS rises with TCK or when TDI rises with TCK.

I'm using a Bitblaster and have fitted a 1 kΩ resistor between TCK and ground and the remaining three lines have a 1 kΩ resistor to Vcc.

The scope screenshots were taken with TDO routed through a piece of wire straight to the CPLD. I've tried doing this with TCK and the waveforms still have this noise on them. If I try doing the blank check again without changing anything, the noisy bits move around.

Does anyone have any ideas as to why TCK seems to not make it up to the rail, or why TCK and TDO seem to oscillate?

  • 4
    \$\begingroup\$ Can you lower the JTAG clock rate? Most times when you've got poor signals, that lets the signals settle. I've used both 15 MHz and 25 kHz clock rates in the past - and the latter was painfully slow, but it got there! \$\endgroup\$ Oct 5, 2016 at 12:57
  • \$\begingroup\$ Your connections are probably have very inductive loops, consider twisted pairs with ferrite sleeve for CM noise. \$\endgroup\$ Oct 5, 2016 at 13:00
  • \$\begingroup\$ @JohnBurger, I don't know how to slow the clock rate down with this setup unfortunately. It's already only at 50 kHz. I've tried clicking every button and none pertain to clock frequency! \$\endgroup\$
    – mc172
    Oct 5, 2016 at 13:32
  • 5
    \$\begingroup\$ At 500 kS/s the scope will not tell you the truth, the signals look waaay too "rounded" => low pass filtered. Try aquiring less data at a much higher sampling rate. \$\endgroup\$
    – Turbo J
    Oct 5, 2016 at 14:56
  • 1
    \$\begingroup\$ OK, I messed around with the scope settings. i67.tinypic.com/2m5j72t.jpg Yellow is TCK and cyan is TDO. Looks like track inductance to me. What looked like smooth sinusoidal noise before turns out to be 450 kHz or so clock pulses. Thanks Turbo J. \$\endgroup\$
    – mc172
    Oct 6, 2016 at 13:01

1 Answer 1


TCK is generated by programming device, in your case "Bitblaster" device. If both CPLDs behave similar strange way if you connect separately, I would question programming device to be operative. Try another programming device, or another type of device - Byteblaster or USBblaster.

  • \$\begingroup\$ I can't connect separately to each CPLD as they're connected by internal layers and I can't get to the vias, but yes, connecting directly to them sees the same performance. And yes, you're right - it is a Byteblaster - no idea why I thought it was Bit. I tried a physically different Byteblaster and it did the same. \$\endgroup\$
    – mc172
    Oct 5, 2016 at 18:45
  • \$\begingroup\$ Thanks, at least we know that it is not programming device and its cable, and issue is somewhere else - e.g. in measurement as Turbo J proposed. \$\endgroup\$
    – Anonymous
    Oct 5, 2016 at 19:16

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