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I am currently working on a hardware design as a part of my project in verilog. I am fully aware that we usually use the registers to break the datapath which in turn helps us achieve timing closure. However I am not really sure if reading data from the fifo has the same effect.

So basically if I am reading data directly from the fifo and sending it some other module, do I need to register the data to break the datapath or fifo will take care of this ?

Thanks.

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It does break the timing path the same way a register does (presuming the FIFO is proerly designed), but you also have to take the setup and hold times of the FIFO itself into consideration. Usually the setup, hold, and clock-to-output times of standard flip-flops are much better than for the block RAM modules usually used to build FIFOs. This means that you may still have timing issues if, say, the clock-to-output delay of the block RAM in the FIFO is large. You may still need to add flip-flops to the input and/or output of the FIFO module to improve the timing performance.

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  • \$\begingroup\$ You will also get better timing results if you don't use a First Word Fall Through FIFO \$\endgroup\$
    – ks0ze
    Commented Oct 6, 2016 at 12:42
  • \$\begingroup\$ And why is that ? \$\endgroup\$
    – prerna
    Commented Oct 6, 2016 at 17:49
  • \$\begingroup\$ The first word fall through feature basically implements a bypass around the FIFO to decrease the latency of getting data through the FIFO when it's empty. However, this usually requires extra multiplexers and other logic which will further decrease timing margin above and beyond a bare FIFO. \$\endgroup\$
    – alex.forencich
    Commented Oct 6, 2016 at 18:07

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