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I'm trying to understand MOSFET soft switch and I know the more common off-the-shelf configuration is to put the capacitor between gate and Vo. However, I'm trying to understand why I can't do it in another way, that is putting capacitor between gate to ground as the picture shown here. I'm using a PMOS here. Can someone help me understand why I can't do it this way to limit the inrush current to load R6? Here, there is a rocker switch that's normally open and will be flipped to close position to turn on the PMOS. I want to know why putting the capacitor between ground and gate of MOSFET doesn't work. Thanks.

Why is my LTSpice running extremely slow when simulation this circuit at the time the rocker switch is closing??

  • \$\begingroup\$ It works instantly fast for me, no glitches, provided the subcircuit you are using comes from vishay (where I just got it). Which version of LTspice are you using: IV or XVII? At any rate, you can help you convergence by specifying an Rser for the capacitor, by using a negative hysteresis for the switch (.model sw sw vh=-1), by adding an Rser for the source (V4), too. The subcircuit looks clean, I doubt that will be causing any glitches. \$\endgroup\$ – a concerned citizen Oct 6 '16 at 12:15
  • \$\begingroup\$ Thanks. Adding Rser to the source V4 helps. The simulation came out instantly. \$\endgroup\$ – user3618703 Oct 7 '16 at 1:25

Both methods work, but the feedback method works better.


    1. Negative feedback effect reduces the slew rate during switching.

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Note difference in VAR power of filter cap slope and Power in Load R

  • \$\begingroup\$ Are you plotting the power waveform of R and C? Can you add the Vgate and Vdrain(output) waveform? I don't really understand your circuit. Is it the same as mine? I tried to run the simulation of my circuit on LTSpice but it got stuck and became extremely slow during the rocker switch closing action. \$\endgroup\$ – user3618703 Oct 6 '16 at 6:30

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