Now that I'm going to be using the PSoC 5 as my microcontroller of choice, I would like to learn Verilog so I can create my own peripherals for it.
I have spent some time searching the web for Verilog learning resources (especially ASIC World), and I feel I've learned quite a few things about it, however, I also feel that there's a big hole in my understanding. This is because there is something that none of the resources seem to teach.
Once I know the syntax, how do I go about designing a Verilog peripheral?
What I mean is, I'm still baffled by the designs people create in Verilog. E.G. Why did they do it that way, not the obviously much simpler way? For example, I came across this code:
task add; // task definition input a, b; // two input argument ports output c; // one output argument port reg R; // register declaration begin R = 1; if (a == b) c = 1 & R; else c = 0; end endtask
There must be a good reason for the design, but it seems bizarre to me. I get the syntax, I see what it does, but I don't understnd why. Is there some resource for learning to think in Verilog?