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I do have some inquiries regarding using an I2C slave controller (from Arria 10 FPGA).

We are currently assessing MCTP protocol support in our device, whose physical layer is built upon SMBus/I2C, according to MCTP specs. Our starting point would be to use the built-in I2C controller in our fixed processor inside the fpga. Our device would only act as I2C slaves meaning it doesn’t initiate any communication.

I understand that SMBus and I2C have mostly similarities in electrical signal level, except on speeds (SMBus is only up until 100KHz clock, while I2C supports higher clocks; but anyway we are just after basic implementation at 100KHz clock so this is not a concern). However, later on the MCTP specs, it describes the MCTP behavior only in terms of SMBus protocol, like SMBus block write which I don't see exact equivalent protocol in I2C. It also recommended using ARP, which I think is not specified in I2C and only in SMBus. So I'm expecting that the MCTP host will be sending me, the device, commands in terms of SMBus protocol. Now if we have an SMBus controller in Arria 10 this won't be a problem, but we only have I2C, and I'm not sure whether our I2C "slave" controller will understand SMBus protocol. I've tried to research online but I'm getting conflicting views. I've also asked Altera but still waiting for their reply. What I kept on reading is that "SMBus is a subset of I2C".

I'm mostly concerned about multi-byte transactions (block write, read, multi-byte write, whatever their names are), since the host will be sending packets and I will be replying with certain number of data bytes. Will our I2C controller work with SMBus protocol? Let me know what you think.

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    \$\begingroup\$ This answer to a related question may have useful information if you haven't already seen it. \$\endgroup\$ – Roger Rowland Oct 6 '16 at 8:14
  • \$\begingroup\$ Thanks for the link. I've read it. It mostly tackles the case of I2C as master and smbus as the slave; my case is vice-versa - I'm the I2C slave, most likely taking orders from SMBus protocol-abiding master. The link I've read is here. I'm confused since it advises tweaking the SMBus side when I don't have any control there. \$\endgroup\$ – ubermensch Oct 6 '16 at 9:37
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That depends on how much of I2C protocol is implemented in your Arria controller. If it is just reporting the "events" to the program (like "STOP detected", "START detected", "ACK received", "Address received", etc.), then most probably you will be able to implement most of the SMBus, except for maybe ARP which requires, AFAIR, responding to a broadcast address (which your controller may not have support for). The other concern is timeouts. SMBus have stricter timeouts, especially in regard to clock stretching. Compatibility would highly depend on the extent to which the master uses the SMBus protocol and expects conformance.

On the other hand, if your Arria provides a higher level abstraction (like "Send I2C byte"), then it most probably will be a show-stopper.

If you have any evaluation board for your Arria 10 FPGA, I would recommend testing the concept using that board before you go with this chip for design and production.

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  • \$\begingroup\$ I agree, the small low level differences are probably not a problem, but the implementation of the higher level SMBus functions might be a problem. At 100kHz the I2C is indeed not fully compatible with the SMBus. For example the SDA and SCL are allowed to go low at the same time for I2C but not for the SMBus. \$\endgroup\$ – Jot Feb 21 '17 at 21:03

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