# Understand the timing of Shift Register

(I am learning the digital circuit design. Excuse me if this is naive question.)

From the Wikipedia, I found the following diagram about SIPO shift register:

As I understand, this shift register is made of DFF (D Flip-Flop). DFF is triggered at the rising edge of the clock period. So for each rising edge of the Clock signal, the data from the Data In will propagate through one stage of DFF.

My question is, since the Clock is shared by all the DFFs, when the rising edge arrives, all the 4 DFFs must be in triggered/transparent state. So what ensures that the data propagate through only 1 stage of DFF rather than 2 or more stages?

Let's say:

• Td is the internal delay for 1 DFF stage to load data from D to Q.
• Tr is the lasting time of the clock rising edge. See below pic.

I think to limit the propagation to 1 stage, it has to be:

Td < Tr < Td*2

Am I correct?

But in the link above, it says:

In this configuration, each flip-flop is edge triggered. The initial flip-flop operates at the given clock frequency. Each subsequent flip-flop halves the frequency of its predecessor, which doubles its duty cycle. As a result, it takes twice as long for the rising/falling edge to trigger each subsequent flip-flop; this staggers the serial input in the time domain, leading to parallel output.

It makes me confused about a few things.

• What does halves the frequency mean?
• How could a DFF be characterized with a frequency?
• Doesn't a DFF only work at the rising edge of the clock and in general don't care whatever frequency the clock is at?
• And how could frequency be related to duty cycle? Frequency is related to period while duty cycle just means the percentage of one period in which a signal or system is active. I see no relation between frequency and duty cycle.

As Neil_UK said in his reply below, the above wiki quotation is plain wrong. And he has fixed the wiki page.

As EM Fields said in his reply below,

...nothing more can happen until the next rising edge of the clock, since the clock edge that did the work has already died...

Strictly speaking, there's no ideally vertical rising edge. There should be some Tr as shown in above illustration. I guess to limit the propagation of signal through DFF stages, the rising edge must last long enough for the signal to propagate through one stage and short enough for the signal not to propagate through to the next stage.

I just think this kind of control is too tricky/delicate to be true. But if it is true, how is it achieved? (I just placed a bounty for this question.)

• what exactly do you mean by "Tr is the lasting time of the clock rising edge" ? – Elbehery Oct 6 '16 at 10:04
• @Elbehery Thanks for the reply. I added an illustration. Since the clock is shared by all DFF stages, so during the Tr, I think all DFFs should be transparent to input. That's why I think there's a need to control how far the signal can propagate. – smwikipedia Oct 6 '16 at 10:11
• You've been confused by a dud wikipedia entry. See my answer, and see the updated wikipedia page (you may need to flush your browser cache to see the new page) – Neil_UK Oct 6 '16 at 10:25

My question is, since the Clock is shared by all the DFFs, when the rising edge arrives, all the 4 DFFs must be in triggered/transparent state. So what ensures that the data propagate through only 1 stage of DFF rather than 2 or more stages?

Consider the timing requirements of a typical D Flip Flop.

As you can see, there are a number of parameters; of most importance here are setup time, hold time and propagation delay.

The input (at D) must be stable across the period shown (from $t_{su}$ to $t_h$).

For this particular part, the minimum hold time required is 3nsec. This is the minimum amount of time the input must be stable behind the clock for guaranteed performance (i.e. D is transferred to Q)

Any transition of the input after this is effectively ignored by the device. Provided the clock period is greater than $t_{su}$ + $t_h$ it will operate properly.

Now lets look at the propagation delays ($t_{plh}$ and $t_{phl}$)

From the datasheet, these are typically 14 nsec:

As this event will occur beyond the hold time requirement, this transition at the next D input will have no effect as the input is now effectively locked out by the internal feedback mechanism.

Note that the maximum rate a shift register can go is $\frac {1} {t_{su(min)} \ + t_{prop(max)}}$ as the D input must be stable for at least the setup time after the previous Q output has become stable.

Provided the propagation delay is greater than the hold time, it can be ignored for the maximum clock rate.

So the bottom line is that provided the propagation delay from D to Q is greater than the required hold time, a single clock event cannot propagate across more than one flip flop.

Using your diagram, the clock happens at some time $t_0$. The output $Q_1$ will change after the propagation delay of the first flip flop, but as this is going to be after the input setup time at the second flip flop provided the propagation delay of the first flip flop is greater than the input hold time of the second flip flop (it always is, in my experience), then the transition at Q1 (D of the second flip flop) has no effect for this clock event.

That wikipedia link had an incorrect description, it was for a cascaded divide by 2 counter. I have now fixed up the Wikipedia entry so it describes a shift register. It may not be the best description (done in a minute), but at least it isn't plain wrong!

For the timings to work correctly, the hold time on the D input must be smaller then the propagation delay of the flipflop minus the clock uncertainty. As long as this condition is true the new data from the previous flipflop will not change until after the next stage has latched the data.

For an NXP 74HC74 we see from the datasheet that hold time is 3ns worst case, and propagation delay is typically 14ns, so a clock skew of up to 11ns will not case a problem (At 5V) with these timings. Note however that propagation delay is typical not minimum so the margins on a particular part may be much tighter, however for fairly obvious reasons most D flipflops are designed so that this sort of thing works timing wise, as getting a particularly fast one will also likely have shorter hold time requirements.

DFFs are not transparent they operate on the edge of the clock signal. The clock edge has to be fast enough for the circuits to work properly.

An example is shown below:

The first stage is active during the low phase of the clock. When the clock rises the first back-to-back connected inverters (latch) store the current state and the input gets disconnected by the transmission gate left to node X. At the same time the second TG becomes transparent and drives the second latch. As soon as the clock goes low again the second latch retains the value.

In the circuit taken from Wikipedia the flip-flops form a shift register, they all operate at the same frequency. They could be used as counters or clock dividers, however a different configuration would be used for this.

• But, how are you going to achieve 100% symmetrical phi and phi_bar? Probably you would use an inverter, leading at least one gate delay between the two. So now your first transmission gate can pass a '0' a bit longer than a '1', and the second transmission gate can pass a '1' a bit longer than a '0', due to uneven clocks. Similar effects occur with the tristate feedback devices. There is also metal routing between the clock points. Nothing is exact. So this ideal analysis only hides problems that exist in real life. Imo. – jbord39 Oct 9 '16 at 15:46
• @jbord39 -- Of course the timing has to be verified. Making phi and phi_bar symmetrical is not so difficult. If an error margin was needed a delay could be introduced between the two TGs. Routing is only local and very short. Delays are usually determined after parasitic extraction and can be verified as well. Of course there are more robust designs, but I've already seen this one in standard cell libraries. – Mario Oct 9 '16 at 16:50
• Yes, it is in standard cell libraries all the time, it is the most basic DFF. But the clocks are rarely made to be symmetric. 10ps/inverter delay is 'good enough'. The characterization engine will pick up rise/fall differences and reprsent them in tables anyway. My point is that the OP brings up a completely logical question, which has caused real errors in design. Blowing it off as 'at the rising edge it instantly captures it' is a great simplification, but not a very good one imo when the question regards nuance in the timing. – jbord39 Oct 9 '16 at 17:36
• @jbord39 -- My point is, that this design can be made as robust as needed. If this causes an error in the design then the design flow needs to be fixed. Apart from that I think you are reading too much into the question. However, I see your point. – Mario Oct 9 '16 at 17:50

Put simply, there is nothing to prevent the situation you describe except for the designers own knowledge when building it. Keep in mind there is a finite delay between the clock edge triggering and the output changing, usually called clk-to-q or clk-to-out.

With a common Transmission-Gate Style DFF (most used in CPU's today) in today's technology, you would most likely encounter the situation you describe. It is known as a hold violation.

In fact hold violations are the most deadly to digital chips. If there is a setup violation, you can simply slow the clock down until the slow path stops failing. But, if there is a hold violation, there is usually nothing to be done (unless you put failsafe measures such as moveable clock edges per register). Because they are so deadly it is normal to pad furiously to prevent any hold violations. So if you have a cycle path (lets say 400ps @ 2.5GHz) that is only flop->flop; there is no reason to not throw in quite a few buffers. This is in fact encouraged.

Others also stated that DFF's are not transparent. This certainly depends on the DFF, most VLSI FF's today have a transparency of a couple picoseconds. Others are intentionally modified to remain transparent longer (time borrowing flip flop - granting additional time to setup and also forcing you to hold the valid data longer) by delaying the master clock relative to the slave.

If the signal were to jump the flip flop, it would be considered a 0-cycle path. This is typically considered a 'hold violation' which means the data was not held long enough.

The setup and hold times of each flip flop are different. If they were designed for use in a shift register I can almost guarantee you that they will have a negative hold time (delay the clock to the slave latch relative to the master latch; causing the master latch to close earlier and become nontransparent, some time before the slave latch becomes transparent). Either that, or the clk->out of these flip flops may be much longer than the hold time. Or they inserted delay between stages; either on the data path or the clock path (reversed).

It is very simple to fix this problem. In fact there are many, many, many ways to fix the problem. Two simple ones: Just insert an appropriate delay between each flip flop stage. Or, put put a delay between the clock to each flip flop in the shift register; starting from the last in the chain. This will make sure that each flip flop grabs the stable data from the previous flip flop.

This schematic shows the logic of the transmission gates and inverting transmission gates just after the active rising edge of the clock which controls the series of switches with just enough storage capacitance to allow a feedback switch to actively hold that logic level in isolation from the input.

Three (3) stages of D Flip flops are shown below as part or a Shift Register which could be Serial In Parallel Out (SIPO) or Serial In Serial Out (SISO)

Although the clock is inverted for bipolar driving of transmission gates, it is symbolically shown like a relay control for simplified understanding.

simulate this circuit – Schematic created using CircuitLab

This is actually very good question! For how DFF works go here, for clock timing and transition you will find answer here which says the following

Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times.

Implementing this Schmitt action will maximally remove metastability during clock transition. Thus clock will logically rise only once, making trigger check its state only once. For frequency of clock DFFs are usually having min and max values in their datasheets to ensure synchronous signal propagation within its logical elements.

In SIPO configuration your task is to ensure propagation delay through DFF is less than clock period plus some slack to ensure signal is stable in the wire connected to D input of the next DFF.

When the clock input of a "D" type flip-flop goes high, The state of the D input - at that instant - will be transferred to the Q output and Q will remain in that state regardless of any changes in D until the next high-going edge of the clock.

A transparent latch, on the other hand, operates by having Q follow D while the clock is high, and then latching the state of D into Q at the instant the clock goes low.

In the circuit you show, the clock is in parallel with all of the dflops, so once the high-going clock edge appears and the contents of D are transferred to Q - and thus to D of the following stage - nothing more can happen until the next rising edge of the clock, since the clock edge that did the work has already died.

Following is your circuit brought to life with some drivers and its response illustrated with a timing diagram.

Note that the output states of the previous stages are propagated through the following stages only once for each rising clock edge.

• Thanks for the reply. As you said, ... nothing more can happen until the next rising edge of the clock, since the clock edge that did the work has already died. Strictly speaking, there's no ideal vertical rising edge as the Tr in my question indicates. So I guess the rising edge must last long enough for the signal to propagate through one stage and short enough for the signal not to propagate through to the next stage. I just think this kind of control is too tricky/delicate to be true. But if it is true, how is it achieved? – smwikipedia Oct 7 '16 at 0:55

The way it works is that each DFF is enabled for a very short period. To turn a latch into a flip-flop you use something like the following circuit on its enable signal. The clock is connected as the input. When you get the rising edge only a very short pulse is generated. Suppose initially the clock is at 0. The outputs of the NOT gates into the AND gate is high. When you get the rising edge of the clock both inputs to the AND gate are high, generating your high enable signal. However, soon after that the high clock propagates through the not gates and the output of the AND gate becomes low again.

You can time this fairly accurately by choosing the transistor dimensions in the NOT gates. The enable pulse is just the right length for the signal to change once in your shift register, and not to have multiple propagation. This is process dependent of course, and is quite tricky to get right.

• I have to disagree with you on this one. Adding that circuit to a latch just makes it a "pulse latch" : eetimes.com/document.asp?doc_id=1271447 To convert a latch into a flip flop (true FF) you take two latches, put them back to back, and give them opposite phase clocks as the enables. You can do this with any sort of latch. JK, D, SR, etc; it doesn't matter -- the fundamental difference between a latch and a flip flop is in the master-slave topology. – jbord39 Oct 9 '16 at 18:10
• On top of that, it is simply not true. Pulse latches ARE used, but they must be heavily margined because of their more dynamic nature. For example, how you must make sure the pulse is long enough for data to be written at both low and high voltages, across all temperatures and process corners. This is certainly possible, but probably 3-5x more difficult than a traditional master-slave flip flop. – jbord39 Oct 9 '16 at 18:13