Could anyone explain why the output bias voltage of the common source in figure a is not well defined and needs a common mode feedback while the circuit in figure b is well defined?

Here is what I have so far. For the circuit in figure a. When the bias current changes a bit, Vout changes a lot. However, how to explain the same thing for figure b?

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  • \$\begingroup\$ You really need to dive a bit more into this because as it is now you show zero effort in solving this yourself. \$\endgroup\$ – Bimpelrekkie Oct 6 '16 at 14:08
  • \$\begingroup\$ Hi, I have just added what I have so far. \$\endgroup\$ – anhnha Oct 6 '16 at 14:12
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    \$\begingroup\$ Correct, in a Vout is the current difference times the total output resistance Rout. Since Rout is high, only a small current difference makes Vout 0 or Vdd. Keeping Vout on a different voltage requires a feedback loop. \$\endgroup\$ – Bimpelrekkie Oct 6 '16 at 15:18
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    \$\begingroup\$ In b the PMOS diode has a stabilizing effect on Vout. Vout will indeed be Vdd - Vgs2. Now consider what Vgs2 will be over the current provided by M1. Note that M2 is always in saturation, that is a property of the diode (why ?). \$\endgroup\$ – Bimpelrekkie Oct 6 '16 at 15:22
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    \$\begingroup\$ Vgs2 is relatively constant over a wide range of M1 current Indeed, that is the reason. M2 is diode connected transistor so Vgd = 0 that is smaller than Vth Correct again, when connected as a diode, there is no way that Vds can get smaller than Vgs so the transistor must always be in saturation (assuming strong inversion mode). \$\endgroup\$ – Bimpelrekkie Oct 10 '16 at 13:20

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