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I am trying to follow the best practises in laying out a crystal. Namely: 1. Keep traces short and direct 2. Keep it as close to the pins 3. Keep-out region under the crystal 4. No vias 5. Isolate the crystal

However I cannot fit my bypass caps near the pins. Before I change the footprint of the PCB to accommodate the requirement, is there anything I can do to make my current design work?

[update]

The MCU is ATMEGA34U4. Crystals is this

Matching capacitors are 18pF (as per the datasheet in the link).

Not enough space

[Update #2] The following is what I came up with. Thank you all for your eyes on this!

Update

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  • \$\begingroup\$ May I know which software is this? \$\endgroup\$ Oct 7, 2016 at 14:34
  • \$\begingroup\$ How critical are your layout contraints? What frequency are you running at? \$\endgroup\$
    – user98663
    Oct 7, 2016 at 14:36
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    \$\begingroup\$ @b1gtuna, sometimes the best decision is to get close enough to ideal without giving yourself a whole heap more work to do. ATMegas are very tolerant of imperfect xtal placements. What you have here is more than good enough. \$\endgroup\$
    – user98663
    Oct 7, 2016 at 14:50
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    \$\begingroup\$ Are you sure about that 18 nF? Crystal load capacitors from MHz crystals are mostly in the 10-30 pF range.. \$\endgroup\$ Oct 7, 2016 at 15:03
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    \$\begingroup\$ @b1gtuna, that won't be a problem. Have a very close look at your crystal component (literally get a magnifying glass) - you'll notice that it has a very tiny PCB forming the bottom part. That tiny PCB will have a GND plane inside it, shielding your xtal from any signals below. \$\endgroup\$
    – user98663
    Oct 7, 2016 at 16:20

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Your layout looks almost perfect already. If you had place, you could place everything a little bit better, but the influence is so tiny, you will never spot the difference.

Remember, you can built this circuit with THT components on a breadboard and it still works. 16 MHz is not really a lot on a PCB. Trace lengths and length matching are not that important at these frequencies. In any case, make sure that the ground connection is good all around the crystal.

What I would do:

  • move the component right above the crystal to the right
  • move one capacitor in the now free space, leave the other where it is.
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  • \$\begingroup\$ Thanks for your vote of confidence! I will incorporate your suggestions. I have one remaining question. If I route D0 to D3 in the bottom layer, directly underneath the crystal , do you think it is still ok? I would like to avoid signal coupling to the traces, but I guess I need to make compromises. \$\endgroup\$
    – Adam Lee
    Oct 7, 2016 at 15:55
  • \$\begingroup\$ This depends on what these signals are. Do you expect them to change often? If it's a single layer board, you can't provide a good ground connection to the crystal if these traces are below. Maybe move the crystal a bit further to the right to make space for the four traces to run on the left side of the crystal. \$\endgroup\$
    – asdfex
    Oct 7, 2016 at 16:35
  • \$\begingroup\$ Thank you. I have routed them around the crystal to avoid coupling. Please see my updated post. Thank you! \$\endgroup\$
    – Adam Lee
    Oct 8, 2016 at 16:43

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