Section 13.4 of the STM32 Reference Manual (for my STM32F303RE board) states:
The DMA controller performs direct memory transfer by sharing the system bus with the Cortex-M4 ® F core. The DMA request may stop the CPU access to the system bus for some bus cycles, when the CPU and DMA are targeting the same destination (memory or peripheral).
My question is: when exactly are 2 memory destinations the same in this context? Is it only when the 2 actually overlap (e.g. CPU accesses 4 bytes @
A with one instruction - thus accessing
A,A+1,A+2,A+3 - and DMA 1 byte @
A+2) or is the memory split into larger regions and the 2 collide when they're accessing the same region?
If it is the latter, how big are those regions?