Section 13.4 of the STM32 Reference Manual (for my STM32F303RE board) states:

The DMA controller performs direct memory transfer by sharing the system bus with the Cortex-M4 ® F core. The DMA request may stop the CPU access to the system bus for some bus cycles, when the CPU and DMA are targeting the same destination (memory or peripheral).

My question is: when exactly are 2 memory destinations the same in this context? Is it only when the 2 actually overlap (e.g. CPU accesses 4 bytes @ A with one instruction - thus accessing A,A+1,A+2,A+3 - and DMA 1 byte @ A+2) or is the memory split into larger regions and the 2 collide when they're accessing the same region?

If it is the latter, how big are those regions?


2 Answers 2


What this means is that if the DMA and CPU are both targeting RAM, depending on whose turn it is in the bus matrix scheduler, the CPU may be forced to wait for the DMA's turn to be finished.

e.g. If the DMA is doing a ram-ram copy and the CPU is reading/writing to a peripheral register, then they are using two separate bus channels and no waiting happens.

e.g. If the DMA is doing a ram-ram copy and the CPU is reading/writing to ram, then the Busmatrix arbitrates access to the ram. Sometimes DMA will wait, sometimes CPU will wait.

See manual section 3.1 for the busmatrix stuff.

I don't think you'll be able to place your buffers in a memory where the CPU might not compete with the DMA.

  • 1
    \$\begingroup\$ I'd like to add that the DMA and CPU cannot access the same bits in memory at the same time not because some kind of address comparison is being made to see if the bits overlap, but because if both bus masters try to access the same bus slaves (RAM, FLASH, AHB etc.) at the same time they will block each other and take turns instead. \$\endgroup\$
    – jms
    Oct 7, 2016 at 20:07
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    \$\begingroup\$ @jms the point is they can't even both access any part of the RAM at the same time because there is only one address bus going to RAM. No question of any merging when there is an overlap. Its possible to have the RAM split into two regions, but that probably wouldn't be justified on a low-performance part. \$\endgroup\$ Oct 7, 2016 at 21:39

The DMA here is interfacing hardware to memory ports designated for exclusive access.

The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers, DAC and ADC with exclusive access to the DMA memory mapped

  • 0x4002 0400 - 0x4002 07FF (1K) DMA2
  • 0x4002 0000 - 0x4002 03FF (1K) DMA1

Circular buffers are supported in DMA.

  • \$\begingroup\$ Hi Tony, I'm not sure you understood my question. I know how it works (at least from a software perspective) but I'm asking what that specific quoted paragraph means by "same destination" more exactly. I'm asking because I'd like to know where to place a DMA buffer in-memory so that I'd know for sure that the CPU (my software) doesn't collide behind the scenes with the DMA controller accessing that buffer. \$\endgroup\$ Oct 7, 2016 at 19:18
  • \$\begingroup\$ The peripheral addresses and DMA addresses are hard coded spaces. Both end ranges are restricted access from other processes. So say SPI DMA process is created then both the SPI ports and the DMA buffer assigned ranges are restricted from all other non-DMA processes and only DMA access is permitted. These processes can be interleaved and the bus is shared by CPU and DMA controller. If your traffic is bursty then DMA mode makes sense. But if it is regular then DMA does not make sense to enter and exit these modes adds overhead. \$\endgroup\$ Oct 7, 2016 at 19:43

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