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I have been researching USB OTG for a little while and was not able to find an answer to my question. I'm seeking for the conditions, if it's even possible, under which I can have one USB OTG port work in slave mode and at least one USB-A port act as host simultaneously. It is definitely not possible when the two ports are connected to the same USB Hub (e.g. like it is the case with a RPi Zero + Zero4U), but how about when the two ports are entirely separate? Here you can find a 'USB Map' of the Orange PI Plus2:

Orange PI 2 USB map

Could I use the USB OTG port, which originates from USB0, as slave port while, at the same time, using one of the Hub ports connected to USB1 in host mode?

Thank you in advance for your time and for sharing your experiences!

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If they are distinct USB peripherals at least one of which supports mode switch functionality then yes. This is in fact fairly common on dual USB microcontrollers and tablet-type SoC's. Your diagram seems to show such a situation, with one OTG capable dual-role port directly accessible, and a second port setup for host use with a built in hub.

A USB hub tends to be entirely incompatible with usage of any of its ports as a USB device, as operating the USB engine in device mode would be incompatible with operating it in host mode to talk to the hub.

Probably the closest you could come to that would be using a USB data interchange cable plugged into one port of an onboard hub. A data interchange cable is a sort of dual-ended USB device - but one that is generally limited to a particular scheme of data transfer. Of course once you have that pipe supported at both ends, you can push fairy arbitrary data down it.

Theoretically it might be possible to design a hub chip with a single "passthrough" port that could be (while disabling all other ports) reversed to operate as a device and forward data to the SoC's USB interface operating in device mode, but this seems unlikely as a product, as most of the devices where operation as a device is supported don't have space for the connectors from an internal hub anyway. Ultimately in most embedded/dev board settings, the dual USB peripheral on chip approach is preferable to a single port permanently connected to an on-board hub.

Of course in the end USB is not just about hardware, but also about driver stacks and system services, user-mode APIs, etc. There has definitely been hardware that shipped with capabilities not reflect in the software, and it is theoretically possible that a software stack could enforce some kind of limit where both ports would have to be in the same mode. But that doesn't seem too common. An inability to switch modes at all though often is - the mode determination is usually ultimately made by software, which may or may not consider or honor a hardware mode detect input pin.

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  • \$\begingroup\$ This is a general rant with no substance. I flagged it as "not an answer" \$\endgroup\$ – Ale..chenski Oct 10 '16 at 16:00
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The answer to your question is "yes", but attached diagram is incomplete. As a matter of fact, nearly every recent SoC from Intel does have the topology that suports OTG on one port, plus many host ports. The diagram misses an important block "USB Device Controller", which is usually multiplexed at one of USB ports at PHY level (which can be USB3.0 as well),usually at USB0 port. The device controller hardware should be on the top of your picture. Many new tablets do support several USB devices (like touchpads and Bluetooth radios) internally or via external USB ports, and one OTG port, which can change roles. This feature has now full support, both in Windows and mostly under Android.

ADDENDUM: The Allwinner (China) H3 memory map shows two IP blocks for OTG device, and OTG host. The other 3 USB ports are attached to a separate EHCI/OHCI controller. Further OTG description (Section 8.5.1) shows the standard connect topology - two individual blocks are muxed at UTMI bus to a common (internal) UTMI PHY. Just as everywhere else, as in INTEL products. Both OTG IP blocks and other USB host blocks have individual register maps, clocks, and reset controls, and definitely are intended to use simultaneously. The rest is up to embedded software.

So, again, the answer to the main question is unconditional YES, OTG port can be used as slave DEVICE while other USB ports serve as hosts. This is the whole purpose of OTG port in SoC.

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    \$\begingroup\$ You are confusing the diagram provided with a diagram of some other system. In the system covered by the question (which is not an Intel part but rather an ARM, apparently from Allwinner) the USB host (/device) controller and the USB PHY are integrated on the same chip. Perhaps Intel is different, but for most vendors who dominate the SoC space, host and device interfaces for mode switchable ports are not distinct functions multiplexed to the same PHY, but rather one area of silicon that can operate in two different modes. \$\endgroup\$ – Chris Stratton Oct 10 '16 at 4:48
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    \$\begingroup\$ I believe it is you who is confused. The question does not state which exactly processor is it, and the language is used as "e.g. like it is the case with...". Exempli gratia, do you know what it is? More, you probably should not comment on matters way outside your expertise. \$\endgroup\$ – Ale..chenski Oct 10 '16 at 4:59
  • \$\begingroup\$ In fact, the product to which the diagram applies is stated, and the diagram matches the SoC vendor's top level description of their part. \$\endgroup\$ – Chris Stratton Oct 10 '16 at 11:59
  • \$\begingroup\$ Infact both of you are correct. I stated an exact model because this is a board I'm currently looking into buying and hence I'm thankful for a direct answer regarding this product. (EDIT: I though <Enter> would do a line-break). On the other hand, I wanted to expand my knowledge regading this topic so I can distinct between whether it is possible or not for myself, so thank you very much to the both of you! \$\endgroup\$ – M. Häuser Oct 10 '16 at 12:53
  • \$\begingroup\$ Actually, the H3 has somewhat unusual USB feature - it has THREE INDEPENDENT EHCI/OHCI HOST CONTROLLERS, with individual control space and register's sets. It means that the three USB ports don't share USB bandwidth, and can work in parallel, provided that internal memory DMA bandwidth is good enough and is not a bottleneck. This is an interesting feature, unlike Intel Atom architectures with one controller and root hub. \$\endgroup\$ – Ale..chenski Oct 10 '16 at 18:10

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