# How does a computer deal with subtraction of 2 values that are in two's complement?

I'm confused how the computer calculates if there are two values A and B, both are in two's complement. Now we want do the operation D=A-B. How is this done?

Let's say A=0100110 and B=0000111

What we do now?

I would do: 0100110+0000111 but I'm really not sure.

Or maybe: 0100110+1111000? So basically A+NegationOfB

Any ideas? Please let me know as this is very confusing for me...

Edit: jonk I made table for your answer but I don't know how to make in table visible that we have cin0=1 because we have subtraction... you know? is table correct to your description? • How would the first one make any sense? Oct 10, 2016 at 16:38
• I don't know sorry these both are my thinkings and I'd like to know which is right. So it's the second one? Or are both wrong? Oct 10, 2016 at 16:43
• If A is in 2's compliment, you need to take 2's compliment again to turn it into the positive number. Then you add A to B's 2's compliment to get A - B. Oct 10, 2016 at 16:49
• In your example A=38 (decimal) and B=7 (decimal). Do you want to calculate A-B = 38 - 7 or -A-B = -38-7? Oct 10, 2016 at 17:01

In twos-complement, the negation of a number is the same as inverting all the bits and then adding one. So to negate '0100110' just invert the bits to '1011001' and then add '1', giving '1011010'. That's all there is to negation. (I think you know that $\overline{1}=0$ and $\overline{0}=1$, yes?)

Once you know how to negate a value, it's easy to subtract B from A. You just negate B and then add to A. So most computers don't include a separate bunch of logic for subtraction (which would take up space and cost money) but just keep the same ADD capability.

You need to know one more thing. How a basic ripple-carry adder works. Such an adder is built up of a bunch of one-bit adders chained to together. Each one-bit adder accepts one bit from A, a similar bit from B, and a carry-in that comes in from the carry-out of the next-lower-order one-bit adder. Each one bit adder provides a one-bit sum and a carry-out. So there are three bits into the adder ($A_i$, $B_i$, and $Cin_i$) and two bits out ($Sum_i$ and $Cout_i$.) Each $Cin_i$ is connected to the prior $Cout_{i-1}$, so that the carry from the previous sum can be taken into account in the next bit. This is the exact same process you'd do by hand-adding the bits, very similarly to what you learn when adding in decimal.

Now, this fact leaves out what happens for the lowest order bit. What does its $Cin_0$ get? Well, with normal addition where there hasn't been a carry from a previous addition operation, the value for it is '0'. This is what a normal ADD instruction does. There is also a special ADDC instruction, which "adds with carry", so that a carry from a previous ADD can be used in the sum of multiple-word answers. In the ADDC case, $Cin_0 = C$, where 'C' is the carry bit result from the previous ADD instruction.

Now you are set up to understand how subtraction takes place. The ALU usually also has access to both the $Q$ and $\overline{Q}$ outputs for the bits of the inputs to the second parameter for an operation. (Flip Flops have both outputs available, readily.) So there is a MUX (something that can either select from either $B$ or $\overline{B}$.) For subtraction, the $\overline{B}$ is chosen instead of $B$. Then, also in order to perform the +1 needed to finish the negation, the ALU selects '1' as the carry-in by setting $Cin_0=1$. Then it just performs the same old ADD that it always does.

Saves a lot of hardware that way.

A real implementation of an ALU adder will probably not use a ripple-carry adder. Not because they don't work. They do. But because they are kind of slow. You have to wait for all those carry values to ripple over. So there are special "look ahead" methods for making the carry values work faster (more than just one of these ideas.) But the basic idea is all the same, regardless of the exact arrangements used. And the SUB instruction does the same kind of trick in order to avoid having to build up completely different subtractor logic, when the adder can so easily be bent to do the same work.

Consistent with EE.SE, a behavioral schematic would be something like this: simulate this circuit – Schematic created using CircuitLab

The above schematic could be simplified a little by simply placing the ADD/SUB operation control bit (0 or 1) directly into the $C_{in}$ of the adder in order to avoid using the mux. But in general ALUs are a little more complex and there actually is an even wider mux before the $C_{in}$ of the ALU (selecting at least from one of the following four: 0, 1, $C$, and $\overline{C}$.)

EDIT: Your table isn't correct for single-bit addition. I've circled the incorrect parts below: But if the table is for subtracting B from A, then I need some clarification about Cin because subtractors aren't usually built from single-bit subtractors. So I can't give you a direct answer for your table, since I'm not sure about your intent with it.

FINAL NOTE: Work through three or four samples. To do that, make up any A value of 4 bits. Then make up any B value of 4 bits. Take B, invert ALL the bits to their opposite to make $\overline{B}$. Now add $A$ to $\overline{B}$ in the normal way and compute result $R$, tossing away any carry in the result. Now just add '0001' to R. You have your answer now, for A-B.

• Comments are not for extended discussion; this conversation has been moved to chat. Oct 10, 2016 at 19:59
• @Dave Tweed Can other people read this too? Oct 10, 2016 at 20:02
• @klbrtree: Yes, of course. Oct 10, 2016 at 20:05

If you are working in 2's complement, that means that ALL the numbers are in 2's complement form. That is, a positive number will begin with a '0' and a negative number will begin with a '1'

So if A and B are two such numbers and you want to do (A - B), then you 2's complement B and add to A.

• Sadly, I could only give a single upvote. Your answer is both right and concise. Oct 10, 2016 at 17:24
• Ok thanks a lot I understand. Just other question: So if we have A - B and it's said that both are in two's complement, I'll calculate this as you mentioned in the answer. Ok. What if we have just two normal binary numbers A and B and we want do A - B. We would still do it like you said in your answer, right? Oct 10, 2016 at 18:25
• There isn't such thing as a "normal binary number". Two-complement's beauty lies in that "normal binary numbers" are just two-complement's numbers who happen to be positive. Oct 10, 2016 at 19:21

The idea of two's complement is that addition works, even for combinations of positive and negative numbers. If you count (in 3 bits) 000 001 010 011 etc. what comes before the 000? Well obviously, 111, because if you add 001 to 111 you get 000. So that is the value for -1. So the value list (for 3 bits) is

 3 : 011
2 : 010
1 : 001
0 : 000
-1 : 111
-2 : 110
-3 : 101
-4 : 100


It is just the normal (unsigned) counting order, but the list is not 000 ... 111 but 100 .. 011. If you regarded the list as circular, those two list are just different ways to cut the circle into a straight line. That is why the same calculation unit (specifically: the addition hardware) can work with unsigned or signed numbres, without even knowing which it it dealing with (except for overflows).

Did you learn how to calculate the bit pattern for -x when given the pattern for x? The method is

• flip all bits

so to calculate -2 in 3 bits start with 2 in 3 bits, which is 010. Flip all bits to get 101. Now add 001, to get 110. Which happens to be -2 in the list. Hurrah! Don't try to understand this process, just learn it.

Now how would an ALU caculate x - y? Doesn't have to. It cpould calculate - y (using the above process), and x + z. So in effect could calculate x + ( - y ). Older ALU hardware realy did this in two steps (because the adder hardware was the most expensive part, so the ALU had only one instance of it).

The simplest way to reason about two's complement is to consider three principles:

1. The lower bits of the sum, difference, or product of any two values will be unaffected by any higher bits in the operands.

2. For any value k, subtracting 1 from a number which ends with k zeroes will yield a number that ends with k ones; this principle generalizes to the idea that subtracting 1 from 0 yields an infinite number of ones.

3. If defines sign-extension of a k-bit number to l bits as prepending l-k copies of the left-most digit, the effect of sign-extending two k-bit values to l bits before adding, subtracting, or multiplying them will be the same as performing the operation on the lower k bits and then sign-extending the result provided that the first l-k+1 bits of the result would all match (i.e. it's numerically within the range that can be represented by sign-extended k-bit values).

Understanding the above will make other properties of two's-complement numbers (e.g. the fact that the value of the sign bit is inverted, negating a value is equivalent to inverting all the bits and adding 1, etc.) fall into place.