10
\$\begingroup\$

I have a 6-layer board where the internal 4 planes are +15,GND,VCC,-15. I was wondering if there was any advantage to doing a copper pour on the top and bottom layers? I would probably leave them floating as I don't want to use micro-vias to say tie it to GND?

Is this actually a bad idea? I.e. floating copper=antenna.

Would it be just as acceptable to have 4 layer board with the top layer having copper pour to VCC and the bottom having a pour to GND and keep the two internals as +-15?

Note that this is for a fairly low speed circuit which has some analog and digital parts.

\$\endgroup\$
3
\$\begingroup\$

Typically outer layer pours are a bad idea. Outer layers have lots of components and traces that tend to chop up the pour. Little islands of pours lead to EMI issues.

If you do a star topology for your +5V (branch from the supply rather than creating loops) with really thick traces (0.020" min) then you could possibly do away with a couple of pour layers. It will certainly reduce board costs. Depending on your supply usage, you might be better pouring the GND and delivering one of the 15V supplies via traces.

In the end you'll have to build a board to see if it meets EMI, and performance specs.

\$\endgroup\$
  • \$\begingroup\$ Thanks for the input. I've decided to just remove the top and bottom pours and stick to the 6-layer design - It's probably cheaper then spending time trying to reroute a couple of power planes on the top and bottom layers \$\endgroup\$ – Ross W Feb 7 '12 at 19:55
13
\$\begingroup\$

EMC Theory of Copper Pours

Using a copper pour for power and ground planes is a good thing. Using a copper pour on layers which contain signals is dangerous from an EMC standpoint. Why is this?

Using a copper pour on layers which contain signals is dangerous because it's surprisingly easy to create current loops. The induced voltage (external radiation causing a voltage on your trace) and output radiation (your trace causing radiation) are directly related to the area around which the current flows. This relation is known as Ampére's Circuital Law (one of Maxwell's equations, which are the basis of EMC), and can be expressed as

$$ \oint H * d \ell = I_{enc} $$

where \$I_{enc}\$ is the current through the surface defined by the circuit. Making a generous (but practical) assumption that free-space current and magnetic field are uniformly distributed, this means that the induced current is directly related to the area of the surface.

In a normal configuration, this surface is a rectangle running directly beneath your trace on the ground plane. Its width is just the thickness of your PCB. This is quite small!

It's very easy, however, to accidentally develop a board which passes current in a large, circuitous trace with an area of several square inches. Adding copper pour for your supply layers is an easy way to make sure that you don't do this. You can pass vias through this plane without affecting the results much, but cutting this copper pour for a long trace completely negates it's effectiveness.

Two-layer boards often (almost always) share power and ground with the signal layers, so designers usually try to bridge groups of traces with a few vias and a thick trace connecting the broken plane on the other side of the board. The discontinuity introduces some impedance to the path, and this does add some area to the current loop, but it's usually avoidable in boards with more layers for power.

For a multi-layer board, adding a broken copper plane isn't a problem because you can connect the broken plane to the intact internal plane without too much trouble. Just add vias in a 500 mil grid pattern and call it good. Delete any that you need to remove for part placement and trace routing, but remember to add one or two back to compensate for the loss and avoid creating those noxious current loops. I suggest connecting both sides to GND.

Manufacturing Issues with Copper Pours

Another reason to consider adding a copper pour is a purely mechanical problem. Copper plating a PCB on one side only can cause the FR4 base to warp (which is bad). For this reason, PCBs often have a hatched plane on areas which have markedly lower trace densities.

For your multi-layer board with separate power and ground planes, it's reasonable to expect that the copper density on each layer will be fairly consistent across the surface of your PCB. You shouldn't have to worry about this.

Enough theory and background! What's the answer?

In your situation, I'd probably just skip the copper pour. You've already got power and ground planes, so you'd gain little in the layout steps and EMC problems.

If you want to add it for appearance, to have the extra ground connections for probing or rework, to improve your EMC characteristics, or to add additional heat sinking, you should connect it to ground. You state I don't want to use micro-vias to say tie it to GND but that's precisely what should be done. Assuming you're not manufacturing the board, these vias will be cut by machines. It probably won't cost you anything (they don't need to be micro vias...), and it won't add much time to the layout process.

\$\endgroup\$
  • \$\begingroup\$ Thanks for the detailed comments - Much appreciated. I've gone with just removing the top and bottom pours. \$\endgroup\$ – Ross W Feb 14 '12 at 16:39
0
\$\begingroup\$

If you do pour the copper pour planes for EMI shielding purposes only, then do not pass any current in the top or bottom pour plane. Make it a NO-NET. Then add a via to connect it to it's internal GND plane inside board layers. The VIA won't initially want to connect, so pour a small copper fill over the via and poly and it will now connect to that one via.
If you too many vias, you may now be passing currents and creating loops, which is not good.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.