The numeric_std.vhdl says this:
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; type SIGNED is array (NATURAL range <>) of STD_LOGIC;
Does this means that the unsigned and signed have std_logic as their subtypes?
Why then is it that when I have an entity with a port of signed or unsigned type and I connect a std_logic_vector(3 downto 0) to it, I get an error?
component dummy is port( a: in std_logic_vector(3 downto 0); b: in signed(3 downto 0); c: in unsigned(3 downto 0); d: out std_logic ); end component;
If I port map a std_logic_vector to b or c I get errors:
Signal "b" is type ieee.std_logic_1164.STD_LOGIC_VECTOR; expecting type ieee.NUMERIC_STD.SIGNED.