# Confused how to derive output voltage from Op Amp and RC circuit

So I'm trying to solve the following question:

I'm very confused how they derived the equation for the output voltage. It was from my understanding that for an ideal op amp, the current through the positive terminal (because it's non-inverting) is $0$. Therefore, the current through the resistor $R1$ should be the same current through the capacitor. So how does any current flow through the 1k ohm resistor or $R2$? Because if any current did flow, wouldn't that violate KCL for the node on the bottom to which the source voltage, the capacitor, ground, and the 1k ohm resistor are connected to?

• The Op Amp has sufficient gain to drive output so that Vin-=Vin+ Commented Oct 11, 2016 at 16:40

There are hidden power supplies connecting from the ground node to the positive and negative supply pins of the op-amp. Current to the output pin of the op-amp flows from these supplies.

I'll redraw the circuit including these supplies:

simulate this circuit – Schematic created using CircuitLab

Now can you see how current from the op-amp output can flow back to the op-amp's positive supply pin?

• So there is current flowing through the 2 resistors on the right? Then where does this current flow back to? Because the current flowing from the output pin must flow through R2 and the 1k resistor, then where does the current goes when it reached that bottom node? It cannot go left because then KCL will not be satisfied. Commented Oct 11, 2016 at 16:39
• It flows out the op-amp's output pin, through R2, through R1 to the ground node. Then through the (not drawn) power supply to the op-amp's (not drawn) positive power pin, through the op-amp to the output pin. Commented Oct 11, 2016 at 17:42
• Where is the 1k ohm resistor? Is that R3? Commented Oct 11, 2016 at 17:59
• @VishwaIyer, I edited to match the way the resistors are labeled in your diagram. Commented Oct 11, 2016 at 18:00
• So the wire connecting the 1k resistor and the middle node in the diagram i provided, is that negligible? so we are supposed to assume the current through it is 0? Commented Oct 11, 2016 at 18:05