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I am routing some external signals through an Altera FPGA and noise is coupling into the signals from something else in the FPGA. I have an idea to physically distance the signal route from the rest of the hardware and then have a ground separating the two sections of the FPGA.

Is this possible? Has anyone ever done this?

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    \$\begingroup\$ "noise is coupling into the signals from something else in the FPGA" is it your theoretical assumption, or you have proven it to be the case? \$\endgroup\$ – Anonymous Oct 11 '16 at 21:02
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    \$\begingroup\$ I've never heard of anyone doing it. Even if you can place the signals in Altera's version of FPGA Editor, or floorplanner, it may not work if e.g. power supplies carry the noise. If the signals are that critical, keep them outside the FPGA. \$\endgroup\$ – Brian Drummond Oct 11 '16 at 21:05
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    \$\begingroup\$ You have p̶r̶e̶t̶t̶y̶ ̶m̶u̶c̶h̶ ̶n̶o̶ ̶c̶o̶n̶t̶r̶o̶l̶ very limited over where the routing goes, so you can't route a "ground plane" inside the chip. What exactly is the signal you are trying to pass (frequency, shape, etc.) and what do you mean by noise (jitter? etc.). You are asking an X-Y question - you are telling us what you think the solution should be, rather than telling us about the actual problem. \$\endgroup\$ – Tom Carpenter Oct 11 '16 at 21:16
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    \$\begingroup\$ What you are probably seeing is noise generated by insufficient decoupling of the power pins driving the I/O bank that is outputting your signal. As a result the power supply noise is injected onto your output signal. Routing a "ground plane" through the FPGA would do nothing at all to fix that. But you'd have to give us more information to go on. \$\endgroup\$ – Tom Carpenter Oct 11 '16 at 21:19
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    \$\begingroup\$ what sort of noise.. analogue or digital glitches? analogue would be more related to the drive strength of the IO wasn't high enough so it was susceptible to "noise" RATHER than "noise" was picked up within the FPGA ... Digital glitches... poor meta hardening of the IO \$\endgroup\$ – JonRB Oct 11 '16 at 21:25
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What IO standard are you using?

3ns would be a big ask for say CMOS33, but should be doable for LVDS depending on the FPGA speed grade and how you have constrained the timing (You have constrained the timing haven't you?).

Altera are a little notorious for sometimes making mixed IO within a bank a complete pain, mixing single ended and differential IO in particular is something that you pretty much need to verify with Quartus before you can actually know if it will work, the rules are obscure and device specific.

Power decoupling is certainly a possible problem, and at these rates you need to be doing impedance controlled layout if the net is more then a few cm long (And termination is a good thing).

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First of all, that signal must be digital in order to be fed into an FPGA. By 'noise' in a digital signal I imagine ringing and spikes. I have never heard of such coupling effect in the standard FPGA fabric. If that effect existed it would be a nightmare and a major issue for FPGA designers. So my educated guess is that coupling happens somewhere else. Pointers I would suggest are:

  • FPGA pins (actually balls) are pretty tight, a signal running next to a clock or high frequency signal can get noise coupled.
  • FPGA not only draw relatively high currents, they also inject HF noise in the supplies, if not decoupled enough, that noise can couple to signals.
  • FPGA usually register signals with a clock, this means edges will become synchronous (delayed) and pulses narrower than a clock period may disappear altogether. That could be called 'noise' by some.
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