What IO standard are you using?
3ns would be a big ask for say CMOS33, but should be doable for LVDS depending on the FPGA speed grade and how you have constrained the timing (You have constrained the timing haven't you?).
Altera are a little notorious for sometimes making mixed IO within a bank a complete pain, mixing single ended and differential IO in particular is something that you pretty much need to verify with Quartus before you can actually know if it will work, the rules are obscure and device specific.
Power decoupling is certainly a possible problem, and at these rates you need to be doing impedance controlled layout if the net is more then a few cm long (And termination is a good thing).