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Modern days, almost any CMOS chip has input clamp diode to clamp their input to the power supply, such as below:

enter image description here

So, in worst input over voltage situation, all energy will finally go to the power supply, right? If the power supply can't sink the current to ground, the power supply voltage will go higher higher, then the entire system will be damaged, what's the proper way to avoid this?

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    \$\begingroup\$ What do you mean under "worst input over voltage situation"? How worst is your worst? \$\endgroup\$ – Ale..chenski Oct 12 '16 at 3:29
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    \$\begingroup\$ Part of a proper power supply is both filtering caps at the output of the PSU and bulk caps near the devices. Both can absorb a certain amount of charge while still keeping rail voltages within tolerance. \$\endgroup\$ – Ignacio Vazquez-Abrams Oct 12 '16 at 7:32
  • \$\begingroup\$ @IgnacioVazquez-Abrams: Yes, transient over voltage may be suppressed by the bulk filter caps at the output of the PSU. What about the sustained over voltage? \$\endgroup\$ – diverger Oct 12 '16 at 11:36
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    \$\begingroup\$ Your device breaks. \$\endgroup\$ – Ignacio Vazquez-Abrams Oct 12 '16 at 11:59
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    \$\begingroup\$ What about add a zener diode to clamp the PSU output? \$\endgroup\$ – diverger Oct 12 '16 at 12:02
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Many ICs are specified to operate normally with sustained current into their IO pin clamping diodes so long as the current is limited. The exact limit is usually specified in the datasheet for the part.

For example a 5V digital signal may go to a 3.3V input if a series resistor is used to limit the current.

There are some types of power supply topologies that are not capable of sinking current. For example many linear regulators cannot sink current.

If you expect to conduct current through the clamping diode, and your power supply cannot sink current, then you have a couple of options.

1) Determine the minimum amount of power supply current that all the chips are drawing from that supply. Then subtract out the expected clamping diode current. If the net current out of the supply is still positive then you don't have a problem since the supply will never be sinking current.

For example if you are running a microcontroller that is always drawing 10mA, and you want to sink 1mA into one of the IO pins then the power supply in the worst case is supplying 9mA instead of 10mA and you don't have a problem.

2) If in option 1 you determine that your clamping current exceeds the other supply currents then you can add a load to ensure that the supply current always remains positive.

For example, if your 3.3V microcontroller is drawing 100uA while sleeping and you want to sink 1mA into an IO pin then you can add a 3.3k load resistor between the supply output and ground to ensure that the net load current is still positive.

3) As an alternative to adding a load resistor, you can add a zener diode or a shunt regulator in parallel with your supply output. The zener will sink the extra current as needed to prevent the supply voltage from going too high. The advantage of the zener over a load resistor is that it uses very little power unless you are actually using it to clamp excess current. Whereas the load resistor uses a higher amount of power contantly.

Care must be used when picking a zener. The zener must have a minimum clamping voltage that is slightly higher than your maximum supply output voltage including all tolerances. The zener clamp voltage also must be low enough that your ICs are not damaged.

For example a 3.3V ± 10% supply that is powering ICs with a recommended operating range up to 5V may use a 4V ± 5% zener.

4) You can use larger series resistors on your IO pins. You will then be sinking less current, at the expense of transition speed. The transition speed is limited by the RC time constant formed by the resistor and the IC pin capacitance. IC input pin leakage current must also be factored in if the resistor is large. For example if the IO pin specifies 10uA of input leakage then using a 10K resistor will change your logic thresholds by 10K * 10uA = 100mV.

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Without clear definition of what is the "worst case overvoltage" and what is its origin, the question does not make sense.

The reference to clamping diodes in CMOS circuits is inappropriate, because this level of protection is designed against the very specific "overvoltage" events, namely ESD (electrostatic discharge) events. The occurring ESD events were carefully investigated and classified by industrial engineering body, which has resulted in several models (machine discharge event, human discharge event). These events are transient in nature, and have limited discharge energy, so the IC protection was designed against them.

If an unspecified "sustained overvoltage" is of concern, then a realistic scenario must be formulated. Otherwise there is no upper limit (100kV electric line anyone? With AWG1 copper bar dropping to PS?) for overvoltage. The proper way to protect electronic devices is to avoid/limit overvoltage externally at its source (AC mains) instead of "protecting PS".

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  • \$\begingroup\$ Agree with you, that e should remove the over voltage from the source. But for lower leakage, I can't afford voltage clampers to ground at the front, I must sink some energy to PS, before I detect the over voltage and remove it. Any suggestions? \$\endgroup\$ – diverger Oct 12 '16 at 23:37
  • \$\begingroup\$ My only idea now is to use a big Ri to limit the input current. And I have differential input, so I should balance the two input branches. \$\endgroup\$ – diverger Oct 12 '16 at 23:41
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    \$\begingroup\$ You really need to explain your ORIGINAL problem instead of asking vague questions about what you think you should do if you want some help. You still didn't explain what do you need to protect, and from what. \$\endgroup\$ – Ale..chenski Oct 13 '16 at 0:01
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You are quite correct that the premise of clamping a signal to a supply rail relies upon that supply rail having a large enough load to conduct away the overvoltage.

Instantaneously, the overvoltage must charge the rail's decoupling capacitance, which will slow its rise time. At the same time, the rail load will draw some of the current. If the rail is supplied by a voltage regulator and the overvoltage is still able to raise the rail voltage, the regulator will, in time, decrease its output to try to keep the rail voltage in regulation.

But if there is no regulator or the rail is too lightly loaded then a zener diode can be put across the rail to conduct away the current if the rail is raised by the overvoltage.

So, as you correctly surmised, the technique of clamping to the rail cannot be taken as a magic transient-remover.

I have recently had PCBs laid out with several lightly-loaded rails that needed this protection. Also, for interest, take a look at the ST USBLC6-2. This IC is to protect a board from transients on the differential data lines of an incoming USB cable. It uses both clamp diodes to the USB 'VUSB' (5 V) supply also on the cable and a zener. The zener allows for protection even when the VUSB supply is lighted loaded and is a good example of what you were looking into.

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