When I read any documents regarding NAND and NOR flashes. They say that NAND is sequential memory whereas NOR is random. I dont understand what stops NAND memory from being random too as the only difference in these two memories are being serial and parallel.

  • 2
    \$\begingroup\$ It would help if you pointed to the documentation you are referring to. \$\endgroup\$
    – st2000
    Commented Oct 12, 2016 at 11:48
  • 1
    \$\begingroup\$ on reads, I'd say NAND flash is an excellent RAM; it's random-access capable just as any modern DRAM, where you'd read a full memory bank at once, too. On write, it's not quite like that, because of the more complex "read whole line, erase whole line, rewrite modified line" idiomatic. \$\endgroup\$ Commented Oct 12, 2016 at 12:39
  • \$\begingroup\$ Careful with the use of the term "RAM" for flash memory. - I got confused for a second, others may too. \$\endgroup\$
    – JimmyB
    Commented Oct 12, 2016 at 15:09
  • 1
    \$\begingroup\$ You may as well ask why your car can't fly because airplanes can and the only difference is one has wings and the other doesn't. They are fundamentally different memory structures intended for different use cases. If you need random access use NOR, if you need cheap bulk storage use NAND. If you need cheap bulk storage with random access the decide which more important because you can't have everything. \$\endgroup\$
    – Andrew
    Commented Oct 12, 2016 at 15:52

1 Answer 1


NAND flash does not store data error free. It has a (comparatively) high bit error rate. For this reason, pages of data in NAND are stored with redundant data that allows for error checking and correction. This means that when you read a byte from NAND flash, it may have an error. In order to check it or correct it, you need to read the whole page of data to get the redundant data. This makes it fundamentally a page-oriented storage medium.

The trend over the last 10 years or so has been for the page size and density of NAND to go up, but the required error correction has also become more complex, and the probability of single-bit errors has also gone up.

The effective time of a read page operation depends on how long it takes to read, check and correct the data. In cases where an error has to be corrected, the effective read time is much longer than the no-error case. This is usually an undesirable characteristic of RAM. The error correction process is computationally intensive, and hardware acceleration is basically required for it to work without hurting system performance.

When it comes to writing data in NAND flash, there are some additional problems. In order to write data, you must first erase. NAND flash does not allow random writing. Erases take a relatively long time, and have to be done on an entire block of pages. So to write one byte, you first need to read a block into volatile memory, then erase it, then write the modified data back (including the newly computed redundant data for the page you modified).

Now we have to talk about endurance. NAND flash can only be erased so many times before it becomes bad. So, sometimes, you go to modify one byte, then find that the block is bad. You have to mark the block as bad, then relocate the whole block somewhere else, just to write one byte. And that means you have to keep track of where blocks have been relocated or remapped to.

I hope you are starting to see some of the difficulties associated with using NAND flash as a RAM.

If you want to research more about this, here are some search terms: NAND flash endurance, NAND flash ECC, NAND flash bad block management.

  • \$\begingroup\$ Also, what if the power goes out while you are relocating a block? \$\endgroup\$
    – user57037
    Commented Oct 12, 2016 at 19:13
  • \$\begingroup\$ When you say "This is usually an undesirable characteristic of RAM", do you mean that RAM has limited to no ability for error correction? \$\endgroup\$
    – Motivated
    Commented Jan 31, 2019 at 17:02
  • \$\begingroup\$ @Motivated, no, I was referring to the fact that read time is variable over a large range. Normally you want RAM reads to be very fast. Some RAM busses do incorporate ECC. \$\endgroup\$
    – user57037
    Commented Jan 31, 2019 at 17:26
  • \$\begingroup\$ If i have understood you correctly, the reason NAND cannot at this stage be random access memory is because of the seek time of RAM? Would it be fair to say that NAND is comparable to RAM when reading data and isn't when writing? \$\endgroup\$
    – Motivated
    Commented Jan 31, 2019 at 17:33
  • \$\begingroup\$ Even a read may trigger an error correction event which will take much longer than an error-free read. So it is not as deterministic, time wise, as RAM. There are things like one-time programmable NAND flash memory which is very similar to ROM. \$\endgroup\$
    – user57037
    Commented Jan 31, 2019 at 17:42

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.