I believe that the "most efficient" and "most inefficient" conditions of LUT-FF pair utilisation refers to how well your design in packed in the logic cells.
Assuming each logic cell has 1 LUT and 1 FlipFlop, the "most efficient" scenario is when you use every logic cell's LUT-FF pair, such that if you have used "L" LUTs and "F" FFs, you used only "C" cells, where
C = L = F
i.e. no resource in any of the cells is wasted.
In the same situation, the "most inefficient" scenario is when you haven't been able to use a single LUT-FF pair, such that using "L" LUTs and "F" flipflops made you use "C" logic cells, where
C = L + F
.i.e. every cell's resource is wasted.
This is of course simplistic as there are other factors including route-through elements & control set restrictions, which are beyond the scope of this answer.
I believe the map report, design_name.mrp will have this detail under the section Slice Logic Distribution.