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I have a system which uses a 3ns pulse to trigger some downstream circuitry. When I hook up the trigger generating circuit directly to the downstream circuit, everything works fine. When I route the signal through an Altera Cyclone V FPGA there is a problem. When I route the signal through a Xilinx Coolrunner II there is the same problem, but it is not as bad.

I can't measure the 3ns pulse well because my fastest scope is 1 GHz (I think the rule of thumb is 5-10x bandwidth for digital signals).

Xilinx Coolrunner II datasheet: http://www.xilinx.com/support/documentation/data_sheets/ds094.pdf

Altera Cyclone V datasheet: https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cv_51002.pdf

The signal is just going in the logic chips and coming out, it is not being manipulated at all.

enter image description here

I had a guess that the input capacitance of the logic chips is the problem, but the Xilinx chip has 10 pF vs the Altera 6 pF, so it doesn't make sense that the problem is worse on the Altera chip.

What settings or circuit parameters affect putting fast pulses through logic chips? I'm expecting to hear things about drive strength and timing constraints but I am not sure and have never messed around with those things.

Thanks in advance, and any feedback on my question asking is appreciated as I am new to stackexchange.

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    \$\begingroup\$ Could you show us the relevant HDL and pin-level constraints for the signal path? If you use an oscilloscope or other appropriate test equipment, how is the signal changed as a result? \$\endgroup\$ – Andrey Akhmetov Oct 12 '16 at 19:10
  • \$\begingroup\$ You can just edit your earlier question. \$\endgroup\$ – Tom Carpenter Oct 12 '16 at 19:20
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    \$\begingroup\$ "There is a problem" is not very specific. What is the specific problem? Does the pulse get wider? narrower? Does it go missing altogether? \$\endgroup\$ – Dave Tweed Oct 12 '16 at 21:33
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    \$\begingroup\$ Why do you have to route it through the chip? If the chip does nothing with it and the output should be the same signal as is input ... why not just use the original signal? \$\endgroup\$ – jbord39 Oct 12 '16 at 21:44
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Page 1 of the Coolrunner II datasheet says that the pin to pin propagation delay is 5.7ns. So any signal you put in is likely to have at least that much delay before coming out.

Also in figure 4 in the datasheet on page 10 we see the IO pin output current for VCC=3.3V. Looking at the curve we see that the IO pin output driver resistance varies non-linearly with the load. The resistance into a short looks like 3.3V/60mA = 55ohms, and further up the curve at Vout=2.0V it is (3.3V-2.0V)/35mA = 22 ohms.

Lets assume the pin capacitance is 10pF on your CPLD, plus another 10pF of trace capacitance, plus another 10pF at your destination. The CPLD pin must drive into 30pF of capacitance.

We can estimate the rise time of the signal using the output resistance of the driver and the load capacitance. Based on the driver resistances we calculated above we see that the time constant lies somewhere between 22 ohms x 30pF = 660ps to 1.6ns. Since both 1.6ns and 660ps are a significant fraction of your pulse width, your signal is likely to experience significant rounding. Also, the peak amplitude is likely going to be less than VCC.

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Regardless of having the signal simply pass through, it passes through logic elements in the FPGA (which gives you the differences in signal integrity between the two FPGAs).

Try adding a pair of flops (for metastability) in the FPGA to capture the input trigger and, as a result, transmit the signal as an output with high integrity. Depending on the clock rate(s) of the other logic in the FPGA, you may have to generate a new clock with a period of less than 3ns/2 for those flops.

This will affect the width of the output pulse, but you can tune that if this path is for you.

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