I have a system which uses a 3ns pulse to trigger some downstream circuitry. When I hook up the trigger generating circuit directly to the downstream circuit, everything works fine. When I route the signal through an Altera Cyclone V FPGA there is a problem. When I route the signal through a Xilinx Coolrunner II there is the same problem, but it is not as bad.
I can't measure the 3ns pulse well because my fastest scope is 1 GHz (I think the rule of thumb is 5-10x bandwidth for digital signals).
Xilinx Coolrunner II datasheet: http://www.xilinx.com/support/documentation/data_sheets/ds094.pdf
Altera Cyclone V datasheet: https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cv_51002.pdf
The signal is just going in the logic chips and coming out, it is not being manipulated at all.
I had a guess that the input capacitance of the logic chips is the problem, but the Xilinx chip has 10 pF vs the Altera 6 pF, so it doesn't make sense that the problem is worse on the Altera chip.
What settings or circuit parameters affect putting fast pulses through logic chips? I'm expecting to hear things about drive strength and timing constraints but I am not sure and have never messed around with those things.
Thanks in advance, and any feedback on my question asking is appreciated as I am new to stackexchange.