I want to model a single one master and two I2C Slaves on a bus. I want to determine how long I can make the I2C Trace to the last/second slave.
How to model the length of the I2C Bus in LTSpice? Should I be using a transmission line model?
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2\$\begingroup\$ This is an unusual goal for a simulation. For a more global picture of the problem, what bus length do you hope to achieve? \$\endgroup\$– dimCommented Oct 12, 2016 at 20:56
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1\$\begingroup\$ Probably this post may be of help, electronics.stackexchange.com/questions/106265/… \$\endgroup\$– Ale..chenskiCommented Oct 13, 2016 at 0:35
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3 Answers
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The length of the I2C bus manifests itself as capacitance, and you can model it as a lumped capacitor. The I2C bus (assuming typical short distances which it's intended for) is way to slow to be concerned with transmission line model.
answered Oct 12, 2016 at 20:46
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Unless you've got a ground plane with a capacitance which the trace works against, The length of the trace manifests itself as inductance, so if you have a problem with delay you should tune it.
answered Oct 12, 2016 at 21:13
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If you need to design your own I2C receivers and want to see now reflections might affect your sampling point, use of transmission line model is always useful and educational. For a fast mode (up to 3.4MHz) the reflections might chew up a significant portion of bit time.
answered Oct 13, 2016 at 0:58