I want to model a single one master and two I2C Slaves on a bus. I want to determine how long I can make the I2C Trace to the last/second slave.
How to model the length of the I2C Bus in LTSpice? Should I be using a transmission line model?
If you need to design your own I2C receivers and want to see now reflections might affect your sampling point, use of transmission line model is always useful and educational. For a fast mode (up to 3.4MHz) the reflections might chew up a significant portion of bit time.