1
\$\begingroup\$

I want to model a single one master and two I2C Slaves on a bus. I want to determine how long I can make the I2C Trace to the last/second slave.

How to model the length of the I2C Bus in LTSpice? Should I be using a transmission line model?

\$\endgroup\$
  • 2
    \$\begingroup\$ This is an unusual goal for a simulation. For a more global picture of the problem, what bus length do you hope to achieve? \$\endgroup\$ – dim Oct 12 '16 at 20:56
  • 1
    \$\begingroup\$ Probably this post may be of help, electronics.stackexchange.com/questions/106265/… \$\endgroup\$ – Ale..chenski Oct 13 '16 at 0:35
1
\$\begingroup\$

The length of the I2C bus manifests itself as capacitance, and you can model it as a lumped capacitor. The I2C bus (assuming typical short distances which it's intended for) is way to slow to be concerned with transmission line model.

\$\endgroup\$
0
\$\begingroup\$

Unless you've got a ground plane with a capacitance which the trace works against, The length of the trace manifests itself as inductance, so if you have a problem with delay you should tune it.

\$\endgroup\$
0
\$\begingroup\$

If you need to design your own I2C receivers and want to see now reflections might affect your sampling point, use of transmission line model is always useful and educational. For a fast mode (up to 3.4MHz) the reflections might chew up a significant portion of bit time.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.