I am trying to understand the usage of ADC sampling time?

The ADC I have has a programmable sampling time of 100nsec/500nsec and 1uSec. What is the primary use case of longer sampling time, why wouldn't you use 100nsec for every signal?

[I also hear sometimes the sampling time is called with alternative names. I am interested in the circuits sample and hold time just before the conversion]

Additional question: what happens if the signal is changing in amplitude during sampling time? If it is falling or rising? Would the ADC take the last position of the signal or does it produce some sort of averaging? If averaging, what is the basis for this, how does it work?

ADC Characteristics:

Capacitor:min 4pF, max:tbd

switch resistance: 1.5K min, 6k max

sampling time: 100nsec, 500nsec (there are longer options but irrelevant)

  • 1
    \$\begingroup\$ A link to the data sheet for your ADC would be very helpful. \$\endgroup\$
    – The Photon
    Commented Feb 8, 2012 at 15:33

2 Answers 2


Many ADC input circuits will connect a capacitor with an unpredictable charge state to the input they're about to sample. If the input is a very low impedance source and won't "budge", this won't pose a problem; that capacitance will quickly match the voltage on the input. If the input is a moderate-impedance source but has very low capacitance, connecting that capacitance may disturb the voltage on the input, but the voltage on the input will relatively quickly return to the correct value. If the input is a high- or moderate-impedance source and has a huge amount of capacitance of its own (e.g. for a 12-bit ADC, it exceeds the sampling capacitance of the ADC by a factor of a few thousand), and if readings are not taken too frequently, the big capacitor may be considered a low-impedance source that won't "budge". If, however, the input has a capacitance that is e.g. 50 times the input sampling cap, then connecting the sampling cap may disturb the input voltage by 1/50 of full scale (a big disturbance) but the increased capacitance may increase 50-fold the RC time constant for its returning to normal.

If the ADC waits long enough between connecting the input capacitance and taking a reading, any disturbance caused by switching the input capacitance will likely settle out. On the other hand, there are some situations where such settling time isn't needed but rapid readings are. Making the acquisition time programmable allows both types of situations to be accommodated.

  • \$\begingroup\$ This is the same thing I was trying to get at in my (deleted) answer, but Jason strongly disagreed with me. Maybe I just didn't go into enough detail or explained it any way that didn't make as much sense. \$\endgroup\$
    – Kellenjb
    Commented Feb 8, 2012 at 18:56
  • \$\begingroup\$ Jason's answer seems pretty good. I can't see yours to comment about it. \$\endgroup\$
    – supercat
    Commented Feb 8, 2012 at 19:13
  • \$\begingroup\$ @Kellenjb: I would undelete; I wasn't disagreeing with the general idea, just with some of the details. (which I think you could remedy with some minor editing) \$\endgroup\$
    – Jason S
    Commented Feb 9, 2012 at 3:27

I assume you are talking about an ADC that has a sampling capacitor (e.g. successive approximation ADC, which is the most common type).

If you're talking about an ADC with a built-in multiplexer, the sampling time is very important, because it allows the voltage on the ADC's sampling capacitor to settle after switching from the previous channel. (More about this issue in a blog entry I wrote.)

If you're talking about an ADC with a single channel, the sampling time is still important, even though it's sampling only one signal, because the voltage on the ADC's sampling capacitor needs to catch up to that signal when it is reconnected to the input, and charged from its previous voltage to the new voltage. If you have a slow-bandwidth input signal, this isn't such a big deal, but if you have a relatively fast-changing input signal, you need to make sure the sampling capacitor catches up to it, by allowing sufficient sampling time.

A more detailed example for single-signal ADC:

Compare your signal frequencies to the sampling frequency. Let's say it's 10kHz sine waves via 100kHz sampling frequency. That's a 36 degree phase shift between samples. Worst-case is when your signal is going through zero (just as the day length changes fastest at the equinoxes rather than at the solstice); sin(+18 degrees) - sin(-18 degrees) = 0.618. So if you have a 1V amplitude sine wave (e.g. -1V to +1V, or 0 to 2V if offset), the difference between samples could be has high as 0.618V.

There's a nonzero resistance between the input pin and the ADC sampling capacitor -- at a minimum, it's the sampling switch resistance, but it can also include external resistance if you have any; that's why you should almost always place at least some local storage capacitor at the input of any sampling ADC. Compute that RC time constant and compare to the sampling time to look at the transient voltage decay after reconnecting the sampling capacitor to the input voltage. Suppose your sampling time is 500nsec and the RC time constant in question is 125nsec, that is, your sampling time is 4 time constants. 0.618V * e^(-T/tau) = 0.618V * e^(-4) = 11mV --> the ADC sampling capacitor voltage is still 11mV off from its final value. In this case I'd say the sampling time is too short. In general you have to look at the ADC bit count and wait something like 8 or 10 or 12 time constants. You want any transient voltage to decay down to less than 1/2 LSB of the ADC.

Hope that helps....

  • \$\begingroup\$ Thanks. My system is probably multiplexed since single ADC engine with several channels. However the particular use case I am interested in is single channel situation. I do not use the multiplexer. I am trying to establish a mental model for the whole thing so I can figure out the corner cases such as if signal is rapidly decreasing during sample time, what happens? \$\endgroup\$
    – Ktc
    Commented Feb 8, 2012 at 13:18
  • \$\begingroup\$ I'll edit to give an example. \$\endgroup\$
    – Jason S
    Commented Feb 8, 2012 at 13:23
  • \$\begingroup\$ Great blog. I need to think about the RC filter in front of my ADC, it is not there now :( \$\endgroup\$
    – Ktc
    Commented Feb 8, 2012 at 13:25
  • 1
    \$\begingroup\$ so let's say max RC = 6K * (4pf*2) = 48nsec. You definitely don't want to use 100nsec sampling time, then; that's only 2*tau. (Or even 4*tau if their sampling capacitance is in fact 4pF.) A 500nsec sampling time, however, is 10.4 tau which would be fine for a 12-bit ADC. (e^10.4 = 33000 = enough for a 14-bit ADC since 2^14 = 16384) As for what external RC.... \$\endgroup\$
    – Jason S
    Commented Feb 8, 2012 at 14:37
  • 1
    \$\begingroup\$ I did some research and some TI app note recommends the cap to be 20x of internal ADC cap. I did more research and talk to the ST guys and it seems 1.5K/8pf worst case which comes out to be 8.3 time constants (just enough for 12 bit). The final question is can I use 50 ohm and 160pf for the RC filter? \$\endgroup\$
    – Ktc
    Commented Feb 9, 2012 at 4:29

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.