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i = 0 & s = 1

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An input of 3rd NAND is 1, 4th NAND input is 0... What will be the second input of 3rd and 4th NAND gate? Why?

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This circuit is known as a gated D-latch. When s=0, a and b are 1, regardless of the value of i, so the output o remains constant. In particular, if o=1, then c=0, and if $o=0$, then c=1.

When s=1, then a = NOT i and b = i. So if i=0, then a=1 and b=0 and hence c=1, which means o = 0. If i=1, then a=0 so o=0, and therefore c=1.

(Notice that c = NOT o at all times.)

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Gate 4 has a zero (b) as one of the inputs, so it outputs a one (c) regardless of the other input. Hence gate 3 will get a one and a one, and its output (o) should be zero.

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  • \$\begingroup\$ Gate 4 has input 0 and 0 ? \$\endgroup\$ – SuMaiL Oct 15 '16 at 12:37
  • \$\begingroup\$ Because b is 0 (one input of gate 4), c must be high. Since c is high and a is high, o is 0, and therefore both inputs of gate 4 are low. \$\endgroup\$ – WhatRoughBeast Oct 15 '16 at 18:17

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