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I'm trying to understand how a transceiver pin can actually operate at, say, 2.5GHz given that the clock speed of an FPGA is so much slower. In my understanding, to transmit data you need to synchronize pulses so that, given that you have a lot of data to send, you 'pulse' for a certain time, and that time is controlled by the clock. Or am I misunderstanding how transceiver pins work?

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The external clock input(s) to an FPGA is typically in the range of 10 to 100 MHz, depending on the application. However, all FPGAs include some number of PLLs (phase-locked loops) that can be used to multiply the clock internally to a much higher value. It is these high-speed clocks that are used to drive the SERDES (serializer-deserializer) logic in the IOBs (I/O buffers — i.e., pad drivers and receivers).

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  • \$\begingroup\$ This appears to conflict with the answer given above. \$\endgroup\$ – Dmitri Nesteruk Oct 15 '16 at 20:21
  • \$\begingroup\$ Above what? Remember, the answers don't always appear in the same order. Which answer specifically are you referring to? My answer is in agreement with both Neil_UK's answer and Daniel's answer; we just focus on different details. \$\endgroup\$ – Dave Tweed Oct 15 '16 at 20:44
  • \$\begingroup\$ Also, note that different models of FPGA may have different approaches to implementing high-speed transceivers. \$\endgroup\$ – duskwuff -inactive- Oct 16 '16 at 6:41
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The pins that operate at 2.5GHz (and much higher) are for a SERDES (SERialiser/DESerialiser) that operates completely independently of the FPGA system clock. Link protocols such as HDMI, PCIe and SATA (to name only a few) operate using this type of transceiver.

This is a self-clocked self-synchronising serial single bit interface. As it would be practically impossible to attempt to synchronise multiple paths with a clock path much above a few 100MHz, it forgoes any attempt at synchronising anything to anything.

The serialiser accepts word data from the FPGA, and converts 8 bit bytes to 10 bit words, which introduces enough redundancy so that clock, byte and frame alignment can be recovered at the receiving end.

Where multiple lanes are used for higher link throughput, there is no synchronisation between them at the 2.5GHz level. Data is framed, and lane to lane alignment occurs at the much slower and more practical frame level.

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Specifically in the Altera Cyclone IV gx models (the ones with built-in transceivers) there's an entire analog subsystem responsible for generating PCI Express signals from the reference clock via a PLL system. The power to it has to be filtered and bypassed separately, and it requires some consideration to make sure everything will work in the design.

This is separate from the generic PLLs built into the Cyclone IV which can be used as a clock for the regular logic.

In the case of the Cyclone IV, there is hardware after the transceiver that collects the serial data into lower rate but wider (32-128 bit) transactions for transmission on the internal bus.

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  • \$\begingroup\$ This happens to be the model I'm planning to use. How can I get the data rate from the frequency though? If I have a 2.5Ghz pin, does that mean that I can transmit 2.5Gbits/second on this pin? \$\endgroup\$ – Dmitri Nesteruk Oct 16 '16 at 8:08
  • \$\begingroup\$ With PCI Express there is an overhead involved with the error correction encoding that you need to take into account. The raw transfer may be 2.5Gb/s, but the true data rate won't be. \$\endgroup\$ – Daniel Oct 16 '16 at 8:34
  • \$\begingroup\$ @DmitriNesteruk: the line rate and the true data rate are two different things. PCIe (and others) have line codes. The types of line code often used are 8b / 10b encoding (PCIe at 2.5 and 5Gb/s), 132b / 133b encoding (PCIe at 8G and 16Gb/s). There are of course other types of coding used. \$\endgroup\$ – Peter Smith Oct 16 '16 at 11:15

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