I'm trying to understand how a transceiver pin can actually operate at, say, 2.5GHz given that the clock speed of an FPGA is so much slower. In my understanding, to transmit data you need to synchronize pulses so that, given that you have a lot of data to send, you 'pulse' for a certain time, and that time is controlled by the clock. Or am I misunderstanding how transceiver pins work?
The external clock input(s) to an FPGA is typically in the range of 10 to 100 MHz, depending on the application. However, all FPGAs include some number of PLLs (phase-locked loops) that can be used to multiply the clock internally to a much higher value. It is these high-speed clocks that are used to drive the SERDES (serializer-deserializer) logic in the IOBs (I/O buffers — i.e., pad drivers and receivers).
The pins that operate at 2.5GHz (and much higher) are for a SERDES (SERialiser/DESerialiser) that operates completely independently of the FPGA system clock. Link protocols such as HDMI, PCIe and SATA (to name only a few) operate using this type of transceiver.
This is a self-clocked self-synchronising serial single bit interface. As it would be practically impossible to attempt to synchronise multiple paths with a clock path much above a few 100MHz, it forgoes any attempt at synchronising anything to anything.
The serialiser accepts word data from the FPGA, and converts 8 bit bytes to 10 bit words, which introduces enough redundancy so that clock, byte and frame alignment can be recovered at the receiving end.
Where multiple lanes are used for higher link throughput, there is no synchronisation between them at the 2.5GHz level. Data is framed, and lane to lane alignment occurs at the much slower and more practical frame level.
Specifically in the Altera Cyclone IV gx models (the ones with built-in transceivers) there's an entire analog subsystem responsible for generating PCI Express signals from the reference clock via a PLL system. The power to it has to be filtered and bypassed separately, and it requires some consideration to make sure everything will work in the design.
This is separate from the generic PLLs built into the Cyclone IV which can be used as a clock for the regular logic.
In the case of the Cyclone IV, there is hardware after the transceiver that collects the serial data into lower rate but wider (32-128 bit) transactions for transmission on the internal bus.