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I am trying to get a basic understanding of how VGA port interfacing works.I have started reading SPARTAN 3 VGA Port Interface. I get the function of horizontal and vertical syncs, and the subsequent clock requirements, but I still don't understand the following few lines :

A separate counter tracks the vertical timing. The vertical-sync counter increments with each HS pulse and decoded values generate the VS signal. This counter tracks the current display row. These two continuously running counters form the address into a video display buffer. For example, the on-board DDR SDRAM provides an ideal display buffer. This counter tracks the current display row. These two continuously running counters form the address into a video display buffer. For example, the on-board DDR SDRAM provides an ideal display buffer.

What does it mean by an ideal display buffer? Say, I were streaming "live" video, it would first be stored in the on-board DDR SDRAM? How do the two continuously running counters form the address (is this the address where each pixel's RGB data is stored) into a video display buffer?

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  • \$\begingroup\$ Please cite the reference where you got this quote. It appears that either you took it out of context, or you omitted important information, or it is poorly written (or maybe just wrong). In any case your questions cannot be answered based on the quotation as you provided. \$\endgroup\$
    – Richard Crowley
    Oct 16, 2016 at 6:41
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    \$\begingroup\$ @RichardCrowley - the quote is a description of an absolutely standard video frame buffer setup the way just about anyone would build it. Part of the description is repeated, either a copy & paste error in posting it here, or perhaps a mistake by the editors of the source document, but that doesn't change the normality and accuracy of what it says up until the repeat. \$\endgroup\$
    – Chris Stratton
    Oct 16, 2016 at 6:58
  • \$\begingroup\$ Thank you for your input! All of this is from the "Spartan-3E Starter Kit Board User Guide UG230 (v1.0) March 9, 2006". \$\endgroup\$
    – FechP
    Oct 16, 2016 at 11:12

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This documentation is abysmally worded.

Video buffer: An easy way to implement a video buffer is with a dual-port RAM. That way you don't have to worry about fancy timings, etc. and just worry about clocking out pixel data over the video interface.

HS and VS counters: The HS counter sounds like it is tracking the current pixel horizontal location. When the HS counter gets to the max row length, it would trigger a horizontal sync pulse, wait some given time, then start over counting from zero.

The VS counter then should be incremented for each horizontal sync pulse. This will then keep track of the vertical pixel position. When the VS counter gets to the max screen height, it triggers a vertical sync pulse, waits some given time (flyback time), then starts counting over from zero.

Because you have these two counters keeping track of where the current pixel is, the current pixel RAM address is going to be:

Pixel RAM address = VS * row_length + HS

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  • \$\begingroup\$ Actually the documentation is fairly accurate - in some key respects more accurate than what you have written. But it is intended to document rather than to explain. When you write "it would trigger a horizontal sync pulse, wait some given time, then start over counting from zero" you describe something hard to implement in an FPGA - what the code describes is a counter with a decoder - it is the decoder which creates the pulse and the "wait" based on the count. It is probably proposing the external DDR SRAM because enough internal dual-port RAM for color VGA gets expensive. \$\endgroup\$
    – Chris Stratton
    Oct 16, 2016 at 7:02
  • \$\begingroup\$ @ChrisStratton If you know so much about it, you should write an answer. Maybe you can get some more rep out of it. OP clearly has no idea how a video buffer works, so this is meant to be a very general description. \$\endgroup\$
    – Daniel
    Oct 16, 2016 at 7:21
  • \$\begingroup\$ I have seen code where the horizontal and vertical sync pulses are manually triggered when the respective counters reach max values.I understand the front porch, back porch, pulse width times.How exactly is this syncing being done with a decoder? And from what " VS * row_length + HS", I get that this is a long array of addresses? Will these pixels be flushed out as the corresponding information is displayed? I realize that this might be excessive, so, feel free to refer me to any link that explains this. \$\endgroup\$
    – FechP
    Oct 16, 2016 at 11:22
  • \$\begingroup\$ No, the point of a framebuffer is that everything stays put until you overwrite it. The SDRAM makes it more complicated than a dual port RAM would be because you need to schedule the writes for areas where you aren't currently reading out I believe. \$\endgroup\$
    – Daniel
    Oct 16, 2016 at 15:13
  • \$\begingroup\$ The way I read it, the decoder is just looking for a timer value and triggering an action when a certain value is achieved. \$\endgroup\$
    – Daniel
    Oct 16, 2016 at 15:13

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