I have fabricated NMOS and PMOS devices on simulation using Silvaco software, the fabricated device (CMOS) is shown below. enter image description here Now, I want to find the dynamic power dissipation of the CMOS inverter by applying a pulse to the input and I'm getting right behavior as you can see in the figure belowthe figure shows the input signal (V[1] and the output signal transient response V[3])

I used the following command in my code:

vin 1 0 0. PULSE 0 1.2 0 1ps 1ps 500ps 10

The input signal is vin, a pulse signal goes from 0 to 3V, the rise and fall times are 1ps and the pulse width is 500ps. I used 0.1pf as the load capacitor. The supply voltage VDD is is 1.2V.

However my advisor asked me to change the rise and fall times to the typical corresponding values in 90 nm technology. Unfortunately, I could not find a clear answer to my question, and I found some researchers are using values according to their applications. Could you please provide me with a good trusted reference?

  • \$\begingroup\$ One approach would be to search for process sizes corresponding to various FPGA lines (e.g. what process was the Spartan-3? and the Virtex-4? from Xilinx) Just google "90nm FPGA" and look at the first few links. Once you find a couple of matching FPGAs, you'll find pretty good documentation on their internals in their datasheets \$\endgroup\$ – Brian Drummond Oct 16 '16 at 11:12
  • \$\begingroup\$ To add to Brian Drummond's comment, the Xilinx families on 90nm are all the Spartan 3 series (3, 3A, 3E) and Virtex 4. \$\endgroup\$ – Peter Smith Oct 16 '16 at 14:57
  • \$\begingroup\$ Thanks Mr. Drummond and Smith for your prompt answers :) I'm doing analog not digital, does it make any difference? I'm not using FPGA or Xilinx, I did the device fabrication on Silvaco software. \$\endgroup\$ – Rana Mahmoud Oct 17 '16 at 9:19

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