I have fabricated NMOS and PMOS devices on simulation using Silvaco software, the fabricated device (CMOS) is shown below. Now, I want to find the dynamic power dissipation of the CMOS inverter by applying a pulse to the input and I'm getting right behavior as you can see in the figure below
I used the following command in my code:
vin 1 0 0. PULSE 0 1.2 0 1ps 1ps 500ps 10
The input signal is vin, a pulse signal goes from 0 to 3V, the rise and fall times are 1ps and the pulse width is 500ps. I used 0.1pf as the load capacitor. The supply voltage VDD is is 1.2V.
However my advisor asked me to change the rise and fall times to the typical corresponding values in 90 nm technology. Unfortunately, I could not find a clear answer to my question, and I found some researchers are using values according to their applications. Could you please provide me with a good trusted reference?