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Is it possible to "comment out" a circuit in LTSpice in the same way that it is possible to "comment out" a directive? Such that it is visible, but ignored during simulation.
Example use cases:
There's no simple answer other than manual disconnectioin. Even this can be tricky depending on what you're simulating. This is one of mine:-
The random voltage source (B1) has been disconnected and a sine wave (V4) applied. This worked for me as all I was interested in was the output signal. Unless you're simulating a Xeon processor out of discrete transistors, I've never had a time problem just allowing the computer to simulate lots of components, even if not required. You can always have a gin whilst waiting.
The problem arises though if you're looking at things like power consumption. Clearly Power will still be consumed if you disconnect an unwanted signal from an unwanted module. So you disconnect it at the power side. That might then leave the output end (with all its impedance s and conduction paths) possibly affecting your wanted circuit. This might mess up a gain sweep. So disconnect it at both ends? And if there are other connections? And if there are multiple optional modules?
I don't think that it can be done in more complex cases than my example. Some one mentioned inserting a high value resistor. This is akin to circuit disconnection and brings with it all the problems I outlined above. Even if you set loads of resistors in a parameter list, you'd probably have to spend more time getting that correct than just amending the circuit whole scale.
Thought. Do you always need to disconnect? There are parameter lists, and even the ability to do a Monte Carlo simulation (if you really can't figure out component values). A parameterised list might be suitable in some cases, but there will be some that you just have to redraw.
If you're dealing with subcircuits, it's fairly easy to do it. Suppose that the symbol is Test.asy and Test.sub the subcircuit (or .lib, .cir, .txt, whatever extension you want, it doesn't matter). The instance name is Test. All you have to do is make a dummy subcircuit named Off (for example) which is a blank subcircuit but with the same number of pins (for compatibility with the symbol). If your subcircuit has 3 pins, it would look something like this:
.subckt Off pin1 pin2 pin3
.ends Off
If your subcircuit comes as a load to a current source, or your surrounding elements cannot live without some conducting path, simply add some dummy resistors of appropiate values in there. Then, all there is to do is to rename Test to Off and either comment out the .inc Test,sub or .lib Test.sub statement, if that's what you have, or comment out the whole SPICE .subckt block of text, if that's what you used. This way, you can keep the symbol in the schematic and also keep any parameters you have passed to it, without the need to change/add them again if you were to delete your symbol and then re-add it. The already mentioned methods would also work, but they will keep your node/element count intact (or worse), which means the matrix solver will be burdened, uselessly, even if your subcircuit would hardly ever be used.
If you have hierarchical schematics, I suppose this could be done, too, though I haven't tried this. One way is to make copies. Suppose your file is Test.asc, then only a Test.asy is the symbol linking to the schematic, so you could:
copy/move Test.asc with a new name, Test.asc.orig
create empty Test.asc with only some resistors of high values in it (1G or so)
This will require modifying the files, themselves, so after the test, it would imply renaming Test.asc to Test.asc.off, then Test.asc.orig back to Test.asc, which is a bit tedious, but it can also be done easily with a minor script.
I found simulation very slow in some cases; it could be caused by some problems in the circuits already drew, ok, but where?
I have followed suggestion of other user, and I solved this way:
In this way I was able to find the components of my circuit that slow down the full simulation.
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The practical answer is to either use PSIM/PowerSim (which allows enabling/disabling parts with a hotkey), or PSPICE (which allows enabling/disabling parts by setting a property, which can be scripted to trigger via hotkey). In both tools, the disabled parts show as grayed-out and are excluded from the simulation entirely, avoiding processing power consumption for large sims and enabling the various permutations required when designing complex electronics. I wish LTSpice had this capability, as I can pretty much not work without it...
