0
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Sir,

Whenever i simulate my vhdl code of 4 bit counter in Xilinx vivado 2015.2, i get the error message like following.

ERROR: [VRFC 10-724] found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"

My vhdl code is

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity my_count is
Port ( clk : in STD_LOGIC;
       clr : in STD_LOGIC;
       y : out STD_LOGIC_VECTOR (3 downto 0));
end my_count;

architecture Behavioral of my_count is
begin
    process(clk,clr)
    variable temp: std_logic_vector(3 downto 0):="0000";
    begin
        if(clr='1') then
            temp := "0000";
        elsif(clk='1' and clk'event) then
            temp := temp + 1;
        end if;
        y <= temp;
    end process;
end Behavioral;

test bench is

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity my_count_tb is
    --  Port ( );
end my_count_tb;

architecture Behavioral of my_count_tb is
component my_count
    port(clk,clr: in std_logic;
         y: out std_logic_vector(3 downto 0));
end component;

signal clr,clk: std_logic;
signal y: std_logic_vector(3 downto 0);
begin
    process
    begin
        clk <=not clk after 5ns;
    end process;
end Behavioral;

please help me to solve this error

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1
  • 1
    \$\begingroup\$ temp := std_logic_vector(unsigned(temp) + 1); \$\endgroup\$ Oct 17 '16 at 9:43
4
\$\begingroup\$

Use the type system instead of fighting it.

Any time you see an uncomfortable double type conversion, especially to another type and immediately back again, like

temp := std_logic_vector(unsigned(temp) + 1);

that is fighting the type system, and probably points to a more or less serious mistake in the design.

Instead, think about this:

You want to count - so your data is some form of number, not just a bag of bits.

What range do you want to count? That's not clear from your question, so I'll guess 0 to 15, eliminating negative numbers, covering the 4 bits of output data.

There are 2 obvious choices :

variable temp: natural range 0 to 15 := 0; 
variable temp: unsigned(3 downto 0) := "0000"; 

You are already using the correct numeric_std library for the latter.

Now there will be a suitable "+" operator visible.

What's missing so far is a connection to the output port y.

If you are forced by ridiculous coding standards or a huge existing project to keep all ports std_logic_vector you'll need a type conversion.

y <= std_logic_vector(temp); -- for unsigned temp
y <= std_logic_vector(to_unsigned(temp,y'range)); -- for natural temp

If you are allowed to fix a broken design, consider what y means in the larger context : if it's an unsigned number such as a memory address, use the right type in the port declaration, then the simplest y <= temp; is the correct approach.

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1
\$\begingroup\$

Look here. @A-Kieffer says

In VHDL you cannot use arithmetic operators with std_logic_vector.

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2
  • \$\begingroup\$ this error occuring again even i change std_logic_vector to bit_vector. \$\endgroup\$
    – Varun
    Oct 17 '16 at 8:25
  • \$\begingroup\$ please give the correct code with the test bench \$\endgroup\$
    – Varun
    Oct 17 '16 at 8:31
0
\$\begingroup\$

As stated here.

"You can't increment std_logic directly, you need to convert it to unsigned and the result back to std_logic_vector using the numeric_std package."

@apalopohapa also mentioned it in his comment:

"temp := std_logic_vector(unsigned(temp) + 1);"

architecture Behavioral of my_count is

begin
    process(clk,clr)
    variable temp: std_logic_vector(3 downto 0) := "0000"; 
    begin
        if(clr='1') then
            temp := "0000";
        elsif(clk='1' and clk'event) then
            temp := std_logic_vector(unsigned(temp) + 1);
        end if;
        y <= temp;
    end process;
end Behavioral;
\$\endgroup\$
11
  • \$\begingroup\$ ERROR: [VRFC 10-91] unsigned is not declared ERROR: [VRFC 10-1083] near std_logic_vector ; type conversion expression type cannot be determined uniquely \$\endgroup\$
    – Varun
    Oct 17 '16 at 10:25
  • \$\begingroup\$ errors still present in simulation \$\endgroup\$
    – Varun
    Oct 17 '16 at 10:26
  • \$\begingroup\$ please help me to find the test bench for the following 4 bit counter code.my test bench is not working \$\endgroup\$
    – Varun
    Oct 17 '16 at 12:17
  • \$\begingroup\$ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity my_count is Port ( clr : in STD_LOGIC; clk : in STD_LOGIC; y : out STD_LOGIC_VECTOR (3 downto 0)); end my_count; architecture Behavioral of my_count is begin process(clk,clr) variable temp: std_logic_vector(3 downto 0) := "0000"; begin if(clr='1') then temp := "0000"; elsif(clk='1' and clk'event) then temp := std_logic_vector(unsigned(temp) + 1); end if; y <= temp; end process; end Behavioral; \$\endgroup\$
    – Varun
    Oct 17 '16 at 12:19
  • \$\begingroup\$ What's the error? \$\endgroup\$
    – Doodle
    Oct 17 '16 at 12:35

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