I've read lot of topics here. I read some people saying I prefer to "have CMOS characteristics" & so on , also in some data sheets (like AVR), they say it have CMOS characteristics, etc... I remember once "CMOS compatible" word?

So why having "CMOS characteristics" makes people proud?


7 Answers 7


CMOS (complementary metal oxide semiconductor) logic has number of desirable characteristics:

  1. High input impedance. The input signal is driving electrodes with a layer of insulation (the metal oxide) between them and what they are controlling. This gives them a small amount of capacitance, but virtually infinite resistance. The current in or out of a CMOS input held at one level is just leakage, usually 1 µA or less.

  2. The outputs actively drive both ways.

  3. The outputs are pretty much rail-to-rail.

  4. CMOS logic consumes very little power when held in a fixed state. The current consumption comes from switching as those capacitors are charged and discharged. Even then, it has good speed to power ratio compared to other logic types.

  5. CMOS gates are very simple. The basic gate is a inverter, which is only two transistors. This together with the low power consumption means it lends itself well to dense integration. Or conversely, you get a lot of logic for the size, cost, and power.


It refers to how the gates are constructed on the IC. CMOS stands for Complementary MOS (metal oxide semiconductor), which uses uses both PMOS and NMOS (i.e. complementary) to construct the logic.
CMOS is fast, has a large fan out and uses less power than other technologies.

Other families are TTL (transistor-transistor logic, NPN/PNP still used), ECL (emitter coupled logic - fast but consumes a lot power - still used in varying forms) DTL (diode transistor logic - old), and RTL (resistor transistor logic (older)

"CMOS compatible" or "TTL compatible" is used frequently to describe the voltage levels required for logic 1 and 0.

  • \$\begingroup\$ I may be missing something, but doesn't CMOS stand for just ‘Complementary Metal Oxide Semiconductor’. MOSFET is Metal Oxide Semiconductor Field-Effect Transistor (a mouthful or five). The way I understand it, CMOS logic is made up of MOSFETs, but the two aren't synonymous. \$\endgroup\$
    – Alexios
    Commented Feb 9, 2012 at 23:00
  • \$\begingroup\$ @Alexios - Yes, you're right - fixed. My brain added the FET for some reason - I meant to put just "Complementary MOS" assuming most folk know what MOS stands for. \$\endgroup\$
    – Oli Glaser
    Commented Feb 9, 2012 at 23:09
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    \$\begingroup\$ I think it was not a problem, since MOS describes the used materials, while FET is the physical principle used by the transistor, so I don't think that it's a problem to stick them together. \$\endgroup\$
    – clabacchio
    Commented Feb 10, 2012 at 9:03
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    \$\begingroup\$ @clabacchio - probably not, but it's just for the sake of clarity since it's known as CMOS, not CMOSfet. \$\endgroup\$
    – Oli Glaser
    Commented Feb 10, 2012 at 13:30

Oli and Olin have explained the strengths of CMOS, but let me take a step back.

TL:DR: Complementary logic allows a rail-to rail output voltage swing, and MOSFET transistors are a very scalable technology (billions of transistors can be obtained on a small surface) with some very useful properties (compared to BJT).


The need for complementary gates is due to the fact that the simplest gate concept is based on the idea of pull-up and pull-down; this means that there is a device (a transistor or a set of transistors) which pulls the ouput high (to '1') and another device to pull it down (to '0').

The enhancement nMOS, which is the best performing MOSFET, needs a \$V_{GS}>V_T>0.7V\$ in order to turn on and allow a current to flow; for this reason, it works well as a pull-down device, but not so well as a pull-up (it turns off before allowing output voltage to raise to VDD). Hence the idea to use the pMOS, which performs a bit worse (because holes move slower than electrons, but this is another story) but acts perfectly as a pull-up.

So complementary (the 'C' in CMOS) because you use two device that behave in the opposite way and are thus complementary. Then, the logic is inverting because nMOS (that pulls down) requires a high input voltage ('1') to switch on and pMOS requires a low voltage ('0').

But why is MOS good?

And some additional informations: as Olin also said, the main reason for the spreading of MOSFET technology is that it is a planar device, that means that is suitable to be made on the surface of a semiconductor.

This is because, as you can see in the picture, building a MOSFET (this is a n-channel, the p-channel in the same substrate requires an additional doped region called n-well) basically consists in doping the two n+ regions and deposing the gate and the contacts (very very simplified).


BJT transistors today are also made in MOS-like technology, which means 'etched' on a surface, but basically they consist in three layers of semiconductor differently doped, so they are primarily meant for discrete technology. In fact, the way they are now built is creating these three layers at different depths in the silicon, and (just to give an idea), in recent technology they occupy an area in the squared micrometer order or so, while MOS transistors can be built in <20 nm technology (update this value regularly), with an overall area that can be in the order of about less than 100 nm². (picture in the right)


So you can see that, added to the other properties, a MOSFET transistor is much better suited (in today's technology) to achieve Very Large Scale Integration, or VLSI.

Anyway, bipolar transistor are still widely used in analog electronics, for their better linearity properties. Also, a BJT is faster than a MOSFET built with the same technology (meant as transistor dimensions).


Note that CMOS is not equivalent to MOS: since the C is for 'Complementary', it's a particular (even if widely used) configuration for MOS gates, while high speed circuits often use dynamic logic, which aims to basically reduce the input capacitance of gates. In fact, trying to push the technology to the limit, having two gate capacitances (as CMOS have) at the input is a cause of loss of performance. You could say that it's sufficient to increase the current delivered by the previous stage but, to make an example, 2x charging speed requires 2x charging current, that means 2x conductivity, which is achieved with 2x channel width, and - surprise - that doubles the input capacitance.

Other topologies, like pass-transistor logic, can simplify the structure of certain gates and sometimes achieve higher speed.

About interfaces

Changing topic, when talking about microcontrollers and interfaces, it's important to remember that the high input impedance of CMOS gates makes very important to ensure that Input/Output pins are never left floating (if they have protection, this is ensured internally), as their gate can be exposed to external noise and assume unpredictable values (with possible latch-up and damage). So stating that a device has CMOS characteristics should also advise you of this.

  • \$\begingroup\$ How is single-transistor dynamic logic used in modern designs? I know it was used in NMOS designs like the 6502 or the Atari 2600's video chip, but I would think it would require the use of either passive pull-ups or cycle-based precharge intervals. Passive pull-ups are clearly not going to be energy efficient nor fast, and cycle-based precharge intervals wouldn't seem terribly conducive to speed either. Is there some trick I'm not familiar with? \$\endgroup\$
    – supercat
    Commented Feb 14, 2012 at 23:23
  • \$\begingroup\$ I know the theory, so I don't know who exactly implement it, but probably many manifacturers do. Look out for Domino logic, or NORA logic; in pipelined systems, you can use clocks to drive the precharging phase, and you can interleave it over more stages to use all the edges of the clock. So it's based on dynamic logic, more than passive loading. \$\endgroup\$
    – clabacchio
    Commented Feb 14, 2012 at 23:28
  • \$\begingroup\$ I recall reading about Domino logic in my VLSI course, but it seems a lot of designs are leaning toward pipelining things to have operations on every input clock cycle, and I don't see how that would work with Domino logic. \$\endgroup\$
    – supercat
    Commented Feb 15, 2012 at 0:13
  • \$\begingroup\$ Oh, pipelining and domino logic are perfectly compatible! A domino stage uses only nMOS or only pMOs right? Imagine that you have the cascade of a n-stage and a p-stage: when the clock falls, the n-stage goes in precharge mode while the p-stage evaluates the input...or you can just use registers... \$\endgroup\$
    – clabacchio
    Commented Feb 15, 2012 at 7:10

If you know the alternatives that were there before there was CMOS or before CMOS was fast enough to compete you would understand that it is a great technology.

The alternatives were TTL, LS-TTL, P- or NMOS.

Without the low power consumption of CMOS technology none of the current microprossessors were even close to practical usable.

Todays CMOS microprocessors have a power density (power dissipation per chip area) which is similar to that of a cooking plate. Imagine the power density of alternative technologies would be 100 or 1000 times higher.


Just to add to what others have already answered, one of the reasons a chip-maker will advertise their part is CMOS-compatible, or has actual CMOS outputs, is that means that you can use their chip with all the other CMOS and CMOS-compatible chips.

For example, if you have a microcontroller or FPGA with CMOS I/O pins, then you can use it with CMOS glue logic chips, or a CMOS EEPROM, or a CMOS ADC. Having all these parts use a standardized interface means you (mostly) know you can hook them all up to each other, and they'll work.


CMOS refers to a technology to create integrated circuits (so it doesn't apply to passive devices like resistors). Other technologies exist, like TTL and NMOS.

A big advantage of CMOS is that it uses less power than other technologies. CMOS designs has almost zero static power consumption. Only during transitions does CMOS use a non-negligible amount of power, but even then it's still extremely small as CMOS switches quickly, on the order of picoseconds for the fastest practical designs. (It's why microcontrollers consume more power at higher clock frequencies, as higher frequencies mean more frequent transitions.)

All that means less waste heat and more dense integrated circuits (i.e. smaller IC footprints for the same function). If your device runs on batteries most of the time, or must be as small as possible (e.g. smartphones), this is a huge win.


Basically we are classified logic familys in TWO types 1) unipolar logic familys 2) bipol logic familys the ICs of this family are constructed using unipolar device like MOSFET .hence its also called has mos logic family ex 1) PMOS 2) NMOS 3) CMOS

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    \$\begingroup\$ "Basically we are classified logic familys", I refuse to identify myself as a logic family. \$\endgroup\$ Commented Nov 16, 2017 at 2:31

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