Supercompilation for electronic design

Question

I'm reading Advanced FPGA Design and the first example, one of simply raising a number to the 3rd power, quickly diverges into various quite clever optimizations to make the valuation faster.

Now, personally, I'd argue that such minutae is best left to the computer, so my question is this: is supercompilation (synthetically combining program elements until an optimal algorithm is found) used when appled to HDL?

TBH, I always assumed that that's exactly what synthesis is: taking HDL code and making sure it runs in optimal time. But the book hints at that not being the case, and altering code to shorten the evaluation path actually makes a difference.

Answer 1

Is supercompilation (synthetically combining program elements until an optimal algorithm is found) used when appled to HDL?

Not in the sense of the sort of optimizations described in that book.

Generally speaking, an HDL synthesizer is free to make any optimizations which do not affect the externally visible behavior of the design. They can make changes which improve internal timing, such as refactoring logical expressions, changing internal signals, replicating registers, and even sometimes moving logic across internal registers, but they cannot make any changes which cause a change in externally visible behavior. In particular, any change which would cause a module to take more or fewer clocks to return a result, such as introducing or removing pipeline stages, is strictly forbidden.

In short: HDL synthesizers can make adjustments to a design to allow it to run at a higher clock frequency, but they cannot make changes which make it return a result in more or fewer clock cycles.