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I am reading some specs about Intel CPU. The word bank appears in the following contexts. I am not a native English speaker. Please help me understand its meaning. Thanks.

From the Intel Manual Vol. 3B Chapter 15.1:

The Pentium 4, Intel Xeon, Intel Atom, and P6 family processors implement a machine-check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as: system bus errors, ECC errors, parity errors, cache errors, and TLB errors. It consists of a set of model-specific registers (MSRs) that are used to set up machine checking and additional banks of MSRs used for recording errors that are detected.

And... 15.3.1.1 IA32_MCG_CAP MSR:

MCG_CMCI_P (Corrected MC error counting/signaling extension present) flag, bit 10 — Indicates (when set) that extended state and associated MSRs necessary to support the reporting of an interrupt on a corrected MC error event and/or count threshold of corrected MC errors, is present. When this bit is set, it does not imply this feature is supported across all banks. Software should check the availability of the necessary logic on a bank by bank basis when using this signaling capability (i.e. bit 30 settable in individual IA32_MCi_CTL2 register).

I understand the bank in first quotation just means a bunch of MSR (Model Specific Registers). But what does the bank in the second quotation mean?

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It gives you a big clue in that last sentence. If you search for that particular bit 30, and then back up a bit, you will find some useful information here:

15.3.2 Error-Reporting Register Banks

Each error-reporting register bank can contain the IA32_MCi_CTL, IA32_MCi_STATUS, IA32_MCi_ADDR, and IA32_MCi_MISC MSRs. The number of reporting banks is indicated by bits [7:0] of IA32_MCG_CAP MSR (address 0179H). The first error-reporting register (IA32_M C0_CTL) always starts at address 400H.

See Appendix B, “Model-Specific Registers (MSRs),” for addresses of the error- reporting registers in the Pentium 4 and Intel Xeon processors; and for addresses of the error-reporting registers P6 family processors.

That pretty much tells you that 'bank' in this context means "error-reporting register bank," more specifically.

Which amounts to about what you already guessed, earlier. There are groups of error-reporting MSRs and some systems may have more or fewer of them depending on the functional units present. There is one of these sets for each distinct hardware unit (sometimes just one set of registers may represent a group of hardware units.)

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bank, n. "a set or series of similar things, especially electrical or electronic devices, grouped together in rows." Examples: bank of switches, bank of lights.

Basically, 'bank' means 'group' or 'set'. When it comes to things like memory and registers, there is usually some addressing related connotation, perhaps having to switch between different register banks, or having different register banks for different modes of operation, or having different banks of RAM within a chip, etc.

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A bank in CPU architecture is a range of registers in some addressable space (memory mapped, I/O, or configuration), a set of registers, together with one register that serves as "bank selector". Changing the selector allows to address a different set of registers at the same address space. This mechanism allows to "stack up" several sets/pages of registers in the same address space, saving a lot of linear addressing space.

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