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My intention is to drive a MOSFET (say, a IRF840 or some logic-level) from a low-current (<10mA) SoC output pin.

Using appropriate resistors from gate to pin and ground, this works... but the gate voltage change could be faster.

So I considered putting a NPN (to VCC) & PNP (to GND) BJT between the pin and FET

schematic

simulate this circuit – Schematic created using CircuitLab

and at that point I thought I'd ask if that setup has a name and/or any known problems to avoid (feedback, etc).

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    \$\begingroup\$ Please draw a schematic. You can do it by editing your post, then, after the edit box opens, click on the schematic icon on the top of the text area. \$\endgroup\$ – mkeith Oct 18 '16 at 7:11
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    \$\begingroup\$ The IRF840 is not a logic level MOSFET. \$\endgroup\$ – mkeith Oct 18 '16 at 7:22
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    \$\begingroup\$ What kind of switching rate? Given about \$10\:\textrm{mA}\$ and around \$50\:\textrm{nC}\$, you are already not so slow. Nearing \$100\:\textrm{kHz}\$, accounting for a few tau. BJTs have diffusion charge storage issues when operated as you show them. How fast do you need this to be? \$\endgroup\$ – jonk Oct 18 '16 at 7:38
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    \$\begingroup\$ If you put the PNP on top and the NPN on bottom, you basically have an inverter. The way it is now (emitter follower), you will have a hard time driving near VCC or GND, but it might work. There are special IC's designed just to drive the gate of a MOSFET. If you are interested in that, you can search for low-side gate driver. \$\endgroup\$ – mkeith Oct 18 '16 at 8:08
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    \$\begingroup\$ @mkeith You may never put a PNP on top and NPN on bottom, this will cause a short circuit. \$\endgroup\$ – Marko Buršič Oct 18 '16 at 13:19
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This is called "push pull output configuration" and provides unity voltage gain but significantly low output impedance and high output current. This makes push/pull output ideal for driving high capacitive loads such as power MOSFET gates at relatively high frequencies when the driver (IC or MCU) cannot source enough current --widely used in switching converters (Personally, I'm using this config in my 2-sw Forward and 2-sw Flyback converter designs). No need to place two separate resistors, btw:

schematic

simulate this circuit – Schematic created using CircuitLab

Note that VCC and Vi should be at the same level for proper on/off switching. If, for example, VCC = 12V and Vi = 5V, this circuit cannot perform its job.

PS: IRF840 is not a logic-level gate MOSFET, IRL840 is.

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  • \$\begingroup\$ Thank you very much! So, a quick search gives entries about ringing and spikes on the output. Is this something I should worry about at ~1kHz? \$\endgroup\$ – kaay Oct 18 '16 at 8:19
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    \$\begingroup\$ You're welcome. I'm using this config in my latest SMPS design: Driving 2 power MOSFETs with driving transformer (1P - 2S) at max 130kHz switching frequency. No problem for now in terms of either EMC (conducted or radiated) or functionality. Shouldn't be at ~1kHz as well. \$\endgroup\$ – Rohat Kılıç Oct 18 '16 at 8:27
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    \$\begingroup\$ The circuit is OK, but I think you need a gate resistor from point V0 to the mosfet gate. \$\endgroup\$ – Marko Buršič Oct 18 '16 at 13:22
  • \$\begingroup\$ @MarkoBuršič Due to some kind of ringing, I gather? That's the kind of problem I was asking about, thanks! \$\endgroup\$ – kaay Oct 19 '16 at 13:09
  • \$\begingroup\$ Why VCC and Vi should be same? \$\endgroup\$ – diverger Nov 20 '18 at 10:27
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If you want to keep your high voltage FET, then the following is a common way of the doing the job, and can be driven from 3v/5v logic.

Q1 pulls the signal low through D1. Even with the drop through D1, it gets to more or less as low an output voltage as an emitter follower.

Q2 amplifies the current through R1, so drives the FET much harder than a simple pull up resistor would. Trim R1 to be as big as possible (lowest quiescent current) consistent with driving the FET hard enough. Using a darlington for Q2 may help here.

If the quiescent current in R1 is an issue, then you'd need to use a different configuration. You can buy a CMOS driver that drives a FET gate with several amps, for less than 1£$Euro.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ Interesting, I would try this for a different circuit. Any specific driver chip you'd recommend? \$\endgroup\$ – kaay Oct 18 '16 at 9:04
  • \$\begingroup\$ what is the purpose of D1? \$\endgroup\$ – Sudoer Dec 31 '18 at 17:58
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    \$\begingroup\$ @Sudoer Second paragraph of my answer, first sentence Q1 pulls the signal low through D1. Without it, the capactive load on the output would hold Vo up, then the BE junction of Q2 would get reverse biassed to 5v or so when it would break down, not good. \$\endgroup\$ – Neil_UK Dec 31 '18 at 19:14
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MOSFETS are voltage triggered and therefore they are perfect as they are with your microcontroler or SOC, as long as you use a pull-down resistor to pull the input to ground, you should be fine. Therefore I don't think the complicated NPN and PNP design is required.

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  • \$\begingroup\$ A voltage-controlled resistor. The changes between 'off" and "on" aren't immediate, and adding 2 BJTs is preferable to a larger heatsink. \$\endgroup\$ – kaay Oct 18 '16 at 8:27

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