Ω The safer solution is put a TVS diode to clamp overvoltage, rather than depend on Device leakage effective series resistance. The series R will limit current and AS LONG as that current is safe, continuous, it should be ok. But IF capacitive coupling and ESD protection is compromised, a low Z clamp TVS clamp diode is best (3.6V TVS) to Vcc.
This Answer may use Ohm's Law with some reasonable estimates not precise values.
Probability of failure or infant mortality rises sharply, when ABSOLUTE MAX is exceeded.
MTBF can go from decades of years to microseconds,depending on which parameter and the excess amount.
- Here is how interface current is limited and protected from ESD.
ESD clamp diodes, like all diodes, are rated for certain voltage drop, Vf at some rated current, If and are often in two stages with a series current limiting resistor in between to attenuate 3kV spikes to less than 0.5V or less than the Vgs threshold the CMOS. These ESD diodes are usually limited to 5mA DC current due to the small junction size to get a small reverse bias capacitance of 1pF for fast response of the interface and also fast response of the diode.
Let's assume the ESD rating protection from a standard discharge of 100pF is 1kV @5mA. All Diodes have an internal ESR which is inverse to it's W power rating.
We can estimate the voltage drop on the 1st diode and the voltage drop from the 5mA typical current limit for ESD diodes. If we estimate Vf=1V then we see it could be a 5mW diode (5mA*1V),which has an estimated ESR of 1/(5mW) = 200 Ohms.
But 1kV ESD over 200 Ohms would cause a 5V spike on the 1st diode.
Thus we need a 2nd diode with an estimated 10K in series. Now the ESD spike is 5V/10k= 0.5V which is just enough to be below the Vgs sub-threshold trigger level of CMOS gates.
simulate this circuit – Schematic created using CircuitLab