I am trying to implement t flop using d flip flop in veilog for which my d flip flop code is like this :
module dff(D, CLK, RESET, Q, QOUT); input D, CLK, RESET; // Inputs to flip flop output Q, QOUT; // Output of flip flops reg Q, QOUT; // Flip Flops need to store the previous value, therefore using reg always @ (posedge CLK or posedge RESET) begin // This block executes every time at rising edge of clk or reset if(RESET) // If reset is high begin Q <= 1'b0; QOUT <= 1'b1; end else begin Q <= D; QOUT <= ~D; end end endmodule
And i am using this dff in my t flip flop module which looks like this
module tff(T, CLK, RESET, Q, QOUT); input T, CLK, RESET; output Q, QOUT; wire out1; wire out2; assign out1 = T ^ out2; dff uut(out1, CLK, RESET, Q, QOUT); assign Q = out2; endmodule
But on compiling the code i am getting an error which is Xst:528 - Multi-source in Unit tff on signal Q; this signal is connected to multiple drivers.
Please help me where i am wrong in my code