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I currently have two square wave signals at f1 and f2 (f1 >> f2) that serve as reference signals to two separate lock-in amplifiers that are subsequently connected in cascade to extract the component of the input signal at f1+f2 or f1-f2.

I am interested in attempting to eliminate one of the lock-in amplifiers, by somehow using the the square waves references at f1 and f2 to generate a phase stable reference at f1+f2. This could then be used as the reference for a single lock-in amplifier to directly detect at the intermodulation frequency.

Of particular importance is that the reference at f1+f2 must be phase locked to the precursor reference signals at f1 and f2. The precursor signals are generated by IR photodiodes that measure light passing through a rotating slit, and are thus subject to small drifts due to the slew rate of the motor, air currents, etc.

My problem is, then, how to generate this reference signal. As square waves, mixing the two reference signals (in a double balanced mixer) would yield all the odd harmonics, which for say f1=50~100kHz and f2=1~10kHz would be hard to filter to give just f1+f2 (particularly in a filter without some highly non-linear phase behavior).

Can anyone recommend a good starting point as to how this may be accomplished? Thank you in advance.

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  • \$\begingroup\$ SO you want only the upper IM product for f1=50~100kHz and f2=1~10kHz resulting in 51 ~ 110Khz? when there are lower sidebands 49~99kHz nice try.. How fast do they change? It seems 2 CMOS PLL's is pretty simple but a harmonic lock is pretty hard to select with a tracking filter . A little more detail on f1+f2 usage might yield other simpler methods, \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Oct 19 '16 at 4:29
  • \$\begingroup\$ Type II mixer PLL (HC4046) chip should be much simpler than what you suggest. Then what is done with these two outputs? servo control? or sensor ? \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Oct 19 '16 at 4:34
  • \$\begingroup\$ Thanks for the response Tony! f1 will always wither be 100 kHz or 50 kHz. f2 is freely tunable from 1 ~ 10 kHz. Most often, I will be interested in referencing the signal at 110 kHz as you pointed out (this will be my most used operating condition). The lock-in amplifier that I am using (SR 840) can take a square wave, TTL, or sine wave reference (square or TTL preferred I believe), so having a square wave at f1+f2 would be fine. \$\endgroup\$ – prashpad Oct 19 '16 at 5:25
  • \$\begingroup\$ The thing that I need to avoid at all costs are: (1) Harmonics that are not (f1+f2), 3*(f1+f2), 5*(f1+f2),... (2) loss of phase lock. I am trying to detect the f1+f2 component in my signal of interest signal (and it will be very very weak), and due to the mechanical modulation methods I am using to generate this signal in my experiment, this component will have a certain degree of phase/frequency noise that will necessarily be the sum of the noise in the precursor reference signals at f1 and f2. \$\endgroup\$ – prashpad Oct 19 '16 at 5:30
  • \$\begingroup\$ superhet and IF filter will work but I dont know how you choose f1,f2 \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Oct 19 '16 at 5:54
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You have one reference signal f1 in the range 50k to 100kHz. You have another signal f3 in the range 1k to 10kHz. You want to generate their sum, not their difference, let's call this f3, which will be in the range 51k to 110kHz.

The easiest way is to use a PLL to generate f3. Mix f3 with f1, call the difference f4. Phase lock f4 to f2.

This solves half the problem. The other half is to ensure that you lock to the upper sideband rather than the lower sideband, that f3 > f1. The easiest way to do that is to use a frequency discriminator, to provide a logical output for whether f3>f1 or f3f1, nothing more is done. If f3

There are two sorts of phase detector to use in the PLL, analogue and digital. Each have their own advantages and disadvantages, which bear on what sort of mixer can be used for producing f4.

An analogue phase detector, like a DBM (double balanced mixer) can accept dirty inputs, like using a simple XOR gate to mix f1 and f3, and all of the filtering is taken care of by the loop filter. The disadvantages are that most people these days are only educated in digital circuits, and the gain of the PSD (for loop gain calculations) varies with the input amplitude.

A digital PSD, as providing for example in the 4046 PLL IC, must have clean f2 and f4 inputs. Mixing f1 and f3 to produce f4 when f4 must go up to 10kHz and f1 may be as low as 50kHz requires some fairly steep filtering. It may need an elliptic design with a zero at 50kHz to get clean enough signals.

Given a simple PLL VCO like the 4046, setup the VCO Rs and Cs to cover the f3 range. Design the PLL filter components so the loop will be stable with PSD activity as low as 1kHz. A loop bandwidth of <= 200Hz (<20% of the lowest PSD frequency) is a necessary condition (but not sufficient, read the 4046 apps carefully for the sufficient conditions).

The simplest is the classic 3 state phase detector (yes, it is also used as a PSD), which also acts as a frequency detector. Although the PSDs in the 4046 have independent outputs, their inputs are common, so it's not possible to do both phase detection at f2 and frequency detection at f1,3 on the same part.

Check out US patent US4851784 (now there's a link that should not vanish) figure 4 for an illustration of an all-digital frequency discriminator that can be made with one HC74 and one HC00 (central flipflop uses the other two of the 00 gates!). Ignore the current outputs and take the high/low output (after deglitching with a small RC) from either output of the middle flipflop.

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