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What is the load resistor in the circled stage of the amplifier? If there is a load resistor, what is it's value (either in strict numerical value and/or in terms of the stage's small-signal model parameters (such as gM and r0))?

The stage in question: Schematic with the relevant stage circled

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  • \$\begingroup\$ For the second stage, the load resistor is RC2 = 4k7; but note that, for AC, the input impedance of the last stage (which is equal to approximately \$\beta \cdot r_e\$ due to large R3 and R4) will be in parallel to RC2 and change (decrease) the load resistance of second stage. \$\endgroup\$ – Rohat Kılıç Oct 19 '16 at 5:20
  • \$\begingroup\$ RC2, R4, R5 and Q3's Zin all in parallel. \$\endgroup\$ – Brian Drummond Oct 19 '16 at 10:34
  • \$\begingroup\$ This is a common emitter configuration, the AC gain is "about" Rc2/RE2. \$\endgroup\$ – lucas92 Jan 23 '17 at 19:48
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The load resistor is RC2 for the circled stage. In the schematic it is 4.7K ohms.

The emitter resistor RE2 is bypassed by the C1 capacitor to greatly increase the AC gain of the stage. The DC gain of that stage is ~(4700/1600).

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  • \$\begingroup\$ he wants to know rE for AC gain \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Oct 19 '16 at 3:27
  • \$\begingroup\$ @TonyStewart.EEsince'75 A quick calc and I get AC gains with \$\beta=100\rightarrow r_e=20\Omega, A=235\$ and with \$\beta=200\rightarrow r_e=18.5\Omega, A=250\$, discounting \$C_4\$'s AC impedance and disconnecting \$C_3\$ for the moment. \$\endgroup\$ – jonk Oct 19 '16 at 4:45
  • \$\begingroup\$ I agree and this design loads the output of the 1st stage with βre=100*20=2kΩ so the input signal drops from attenuation with a net gain of 100 due to source impedance of 15k on drain. .. just watching Blindspot TV series... \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Oct 19 '16 at 5:48
  • \$\begingroup\$ I think, all of you have forgotten that the last stage has signal feedback (250||2.2k); hence, the input resistance at the base node of the last stage will be much larger than 2k. \$\endgroup\$ – LvW Oct 19 '16 at 6:12
  • \$\begingroup\$ actually I was referring to 1st stage, but and meant 2nd stage inputZ is 2K thus reduces 1st gain by 2k/15k reduction . but now that you mention 3rd stage I see AC load of 250 Ohms cannot be < DC load of 2.2k without starving emitter of bias current so it ends up half cycle distorted. Emitter follower can source current but not sink current so negative peaks are clipped so Re3 must be less than RL in which case Zin3 = 100*250=25k and Rb3 bias is inadequate, not good choices. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Oct 19 '16 at 6:36
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The immediate load of that stage is RC2, which is 4.7 kΩ.

However, the input of the following stage also presents a load to AC components of the signal. That load therefore does not effect the bias point of the second stage, but does effect its overall gain of AC signals. At sufficiently high frequencies (we can't tell how high since the value of the various capacitors is not shown), the load on the second stage is R3 in parallel with R4, in parallel with the apparent impedance looking into the base of Q3.

From simple observation, we can see that R3 and R4 are "high" relative to the existing 4.7 kΩ DC load. At high enough frequencies, the impedance looking into the base of Q3 is RL reflected back to the base. This is roughly RL times the gain of the transistor. That again should be "large" relative to 4.7 kΩ.

Therefore, the conclusion is that stage 3 presents minimal loading to stage 2, and can be largely ignored, at least for a first pass analysis.

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