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I've generated vhdl from Simple port RAM and Dual port RAM in simulink and I tried to synthesize with Quartus 14 and 16 on Arria V and 10. The option to allow RAM for any size is ON but I don't understand why it isn't recognized. Have you never seen this?

I also synthesized the Altera template with the same data and address and it's correctly recognized. I used matlab 2016

Thank you to all

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The Quartus synthesizer has some serious issues. It's extremely particular about inferring RAMs as well as performing certain constant elaboration (i.e. initializing a RAM with a trig function such as sine). It's infuriating. The most annoying thing is most of this stuff will be properly recognized by the Xilinx tools. I recommend just rewriting it using the provided template instead of using simulink generated code.

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