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I'm currently doing some power analysis for an electronics project and am attempting to make my design more efficient. My design uses a 3V coin cell as it's primary power source. Out of good practice (and because my design operates at 3.3V nominal), I've decided to add a voltage regulator. I've selected this Microchip MCP1252 (http://ww1.microchip.com/downloads/en/DeviceDoc/20001752C.pdf).

This chip is able to be configured as either a 5V regulator or 3.3V regulator. Looking at Figure 2-5, it shows the power efficiency when the regulator is configured to output 3.3V. Looking at my application using a 3V coin cell supply, the regulator is only 55% efficient. This is not that good... However, looking at Figure 2-4, the regulator appears to be much more efficient when configured to be a 5V regulator.

So my question - why is this regulator much less efficient when configured for 3.3V output? Does it have something to do with I^2 R losses? Furthermore, why does the efficiency trend from Figure 2-5 look the way it does? It seems to be much more efficient as soon as you change your input supply to 4V. Why is this?

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It's a charge-pump DC to DC converter and when, theroretically, the input voltage is 2.5V it can charge "the" capacitor up to 2.5V then electrically reposition it to add 2.5V to the input voltage to produce an output voltage of 5V.

This is always going to be its most efficient setup because, if your input supply is (say) 3V and you charged the capacitor fully the output would normally become 6V so, 1V has to be lost (in order to produce a 5V output). This loss is created by not fully charging the capacitor up to the incoming supply voltage in the first place.

Now, with any charge pump voltage generator the losses (inefficiences) occur when charging the capacitor. The lack of an inductor means that these losses are due to internal charging resistors and this is real power dissipation unlike a conventional buck or boost converter.

The biggest loss occurs when initially charging the capacitor - this loss falls as the capacitor charges closer to the incoming supply voltage. This is because the charge current naturally reduces and the resistor \$I^2R\$ power loss falls away.

So, bigger inefficiences occur when the input voltage is slightly less than the required output voltage. Let's say the required output is 5V and the input voltage is 4.9 volts - the capacitor has to be charged to 0.1 volts so it can add (caused by the internal H bridge repositioning it electrically) to the incoming supply to produce 5V at the output. Thus It spends all of its charging time at the most power hungry part of the charge cycle.

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  • \$\begingroup\$ This makes complete sense. And because I'm going from 3V to 3.3V, I'm operating in the fast charging region. Are you aware of any alternative methods for slight DC voltage step-ups? \$\endgroup\$ – Izzo Oct 21 '16 at 17:07
  • \$\begingroup\$ How about sepic? \$\endgroup\$ – alex.forencich Oct 21 '16 at 17:22
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    \$\begingroup\$ @Teague maybe there are some high efficiecy buck-boost chips or you could try bucking down to about 2.1 volts then using the above chip but it strikes me you are not going to get vast improvements whatever you do. You might get 90% efficiency dropping to 2.1 volts from a buck then you'll get 80% from the above chip with an overall efficiency of 72% as opposed to 55% with your current set-up. Not a big gain but you should top 80% with a boost/buck chip. \$\endgroup\$ – Andy aka Oct 21 '16 at 17:23

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