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I am trying to determine the rise time for a component in my circuit. I am unsure if my current method is correct and could use some verification. I would love help in the general case as well.

Case 1: NC7SV86

I am using this XOR gate as a clock inverter. I am powering the device with 3.3 V. I can see from the datasheet that the HIGH level output voltage is 2.2 V, and that the HIGH level output current is -24 mA. Thus (?) the output resistance is:

\$R =\frac{V}{I}= 92\ \Omega\$.

From the datasheet, we also learn that the output capacitance is \$C_{OUT}= 4.5\ \$pF. Thus, the time constant for the output is \$\tau_{RC}=RC=410\ \$ps.

Then, the rise time is \$T_{r}=2.2\tau_{RC}= 910\ \$ps.

Which seems reasonable, but I have no way of verifying. Worrisome, however, because this rise-time produces a knee frequency of: \$f_{knee}= 550 \ \$MHz.

Case 2: 74VCX245

Again, I am powering the device with 3.3 V.

\$R=\frac{V}{I} = \frac{3.3\ V}{100\ mA}=33\ \Omega\$

\$\tau_{RC}= RC = 33\ \Omega\times 7\ pF=230\ \$ps

\$T_{r}=2.2\ \tau_{RC} \ 500\ \$ps

\$f_{knee} \approx 1000\$ GHz

Again, a really high knee frequency.

Do these calculations check out with you all? If not, what is your recommended procedure for determining the rise times.

The target speed for the entire circuit is 100 MHz (clock), so I understand that I will need ground planes and careful impedance matching.

Thanks to Niel_UK, I now see how to use the propagation delay as an order-of-magnitude check, at the least.

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  • \$\begingroup\$ Edgar, I'm bothered by some of the details in your calcs. For example, you compute that \$\frac{3.4\:\textrm{V}}{100\:\textrm{mA}}\$ is \$340\:\Omega\$. I'm also not necessarily agreeing with your first computation about the output resistance. Could you revisit things a little more above and perhaps expand on your reasoning about the output resistance at the top? \$\endgroup\$ – jonk Oct 22 '16 at 5:26
  • \$\begingroup\$ The datasheets provide propagation delays, so why not use those instead? What's important about the rise time? Are you worried about EMI? \$\endgroup\$ – Adam Haun Oct 22 '16 at 5:52
  • \$\begingroup\$ The rise time has to be less than the propagation delay. The propagation delay for the first part is 3ns max at 3.3V. This is with a 500 Ohm/30pF load. This is a pretty fast part. You will probably have sub 1ns rise times if you can keep the loading down to a reasonable level. I am not looking at the second part. \$\endgroup\$ – mkeith Oct 22 '16 at 6:19
  • \$\begingroup\$ Jonk, thank you for pointing out those gross errors. They have been corrected. Adam, I am under the impression that I should impedance match at the knee frequency. Its calculation requires rise time calc. However, please correct me if I'm wrong. \$\endgroup\$ – Edgar P Oct 22 '16 at 7:40
  • \$\begingroup\$ In case 2, why do you use 3.4 V in the calculation when the stated supply voltage is 3.3 V? \$\endgroup\$ – Peter Mortensen Oct 22 '16 at 13:27
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TL;DR you should get sub 2nS rise times from this device, into practical loads

Most of your assumptions and some of your sums are wrong.

To deduce the risetime, that's relevant to the logic situation, you would use the output current into the output capacitance.

The total output capacitance is likely to be the 4.5pF you've identified, plus extra for the pads, traces, and the input of the next load (or loads), so could be much higher. Reckon on 20pF. Buffers that are intended to drive loads are often specified into the loads of 15pF and 50pF.

Charging this output load is your gate output current. On page 3 of the data sheet, the high output is specified to be at least 24mA output, when the output voltage is 2.2v, with a rail of at least 2.7v. This is the minimum, you can expect the current to be higher when the output voltage is lower, say slewing through the critical mid-rail point. How much higher? Some data sheets give graphs of output voltage and current, this one doesn't. So we just know it's higher.

What matters to your downstream logic is the time from a valid logic low to a valid logic high voltage. Traditional RC measurements are not relevant, like 2.2RC, totally meaningless. The low and high input values are specified as 25% and 75% of rail voltage, so you need to time the output voltage through a 1.65v swing, let's say 2v for easier sums and a more pessimistic case.

Let's say your load capacitance is 24pF (so I can do the sums in my head, and also a more pessimistic case). This is being charged at a minimum of 24mA, so at a minimum rate of 1V/nS. This will give you a risetime across 2v of no more than 2nS.

We have to do the down-going sums as well, a gate that swings fast in one direction and slowly in the other is no good to us. Top of page 4, low level output current at 0.55v output, at least 24mA. 0.55v is beyond the valid low logic level, so we can use the same numbers, and obtain a 2nS maximum fall time.

However, is risetime what you should be worried about?

The data sheet does give the propagation delay, and if you look at the timing diagram figure 2, this is specified to 50% output voltage, so includes delay through the gate
plus half the risetime
and has a maximum guarrantee
and is into a practical load capacitance of 30pF with a resistive load as well

I think the reason the data sheet gives a well-specified figure for propagation delay, and is mute on risetime, is it's the propagation delay that designer's use when they are designing a system.

Pro tip. If a datasheet doesn't have figures for what you think you need, and does have figures for something you don't understand, then ask yourself why.

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  • \$\begingroup\$ (+1) Nice back of the envelope reasoning (and I'd add a +1 for the pro-tip if I could! :-) \$\endgroup\$ – Lorenzo Donati Oct 22 '16 at 10:45

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