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I'm designing a board with a ARM Cortex processor (TI Sitara). It needs an external RAM module, and I have never really worked with embedded SDRAM modules in circuit design. Looking at the schematic of the evaluation board for the chosen processor, it can be seen that the eval. board uses 4 smaller RAM modules instead of a single 2GB RAM module.

Are there any advantages of doing that? Also, the "cheaper" RAM modules all seem to have higher CL Latencies (CL-11 @ 800MHz). The board will do real time audio processing, do you think that latency is important in this case?

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  • \$\begingroup\$ Using several SDRAMs instead of just one may be related to refresh timing improvement. With two chips system can run refresh of two arrays in parallel. Then, with two modules you may have only one installed as optional configuration. And in general - two same make chips can be cheaper than one 2x in size. \$\endgroup\$ – Anonymous Oct 22 '16 at 20:13
  • \$\begingroup\$ Cortex doesn't really narrow down the processor much, It could be M0 or A73, without starting to search for that particular part. We can't really answer questions about the workload without far more information. Caches, code size, display memory bandwidth, etc. You can always configure slower timing on your dev board to get an idea about the penalty. \$\endgroup\$ – Sean Houlihane Oct 23 '16 at 13:19
  • \$\begingroup\$ @SeanHoulihane technically my post states that I'm using the processor of the eval. board that I linked the schematic of. The schematic shows a TI Sitara Am4376 ;) \$\endgroup\$ – Xaser Oct 23 '16 at 15:03
  • \$\begingroup\$ The better the information you provide in the question, the better your chance of a good answer, technically correct or not. \$\endgroup\$ – Sean Houlihane Oct 23 '16 at 15:14
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You say "4 smaller RAM modules". I see only two on the schematic and BOM (U6 and U7).

Now, look how they are connected: Their CS (chip select) line are shared (both connected to CS0 of CPU), and their data lane are paralleled (D0-D15 of CPU goes to the first chip, and D16-D31 goes to the second chip).

The obvious benefit of doing this is that you then have a data lane that is 32 bits wide, which provides twice the bandwidth as having a single 16-bit chip with double the capacity. The latency isn't as important as the bandwidth, usually, because there is a prefetch mechanism, some cache in the CPU, and because data is accessed in bursts.

Now, why don't they use a single 32-bit wide DDR3 chip? Because it's not easy to find. Look at digikey, they provide 42 references of 32 bit DDR3 (none of them being stocked, and most of them marked obsolete), versus 359 references of 16-bit DDR3 chips. The standard is just to use 16-bit chips.

For your application, I can't tell you what you need, however. Audio processing, even in real-time, does not usually require amazing performances, and you have something already very powerful for that. Probably, you could go with a single 16-bit chip and the bandwidth would be enough. But if you're really mixing / resampling / etc... a lot of channels, while displaying some information on a high-res screen (with the frame buffer being in the same SDRAM), you may need more. Use your logic to roughly estimate your bandwith requirements (given the audio sampling rate, number of channels, ... and, for the display: screen resolution, color depth, refresh rate, ...).

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  • \$\begingroup\$ One reason is, you are searching for DDR3 rather than LPDDR3/DDR3L. I believe for mobile applications, single chip 32 bit solution, or even POP is very desirable than 16bitx2 \$\endgroup\$ – user3528438 Oct 24 '16 at 15:02
  • \$\begingroup\$ @user3528438 I didn't look much, but after your comment, I tried looking for LPDDR3 or DDR3L with 32-bit wide bus, and it doesn't give any stocked references. \$\endgroup\$ – dim Oct 24 '16 at 15:08

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