If I have traces connecting a relay to an terminal block (10A relay, 6A terminal, 5A expected maximum load) and I double the traces up on both sides of the board (mirror the traces on the top and the bottom) to double the current capacity of the traces (effectively turn 1oz copper into 2oz), is it best to leave them as they are or to stitch the traces together with vias?

The longest trace is just under 1".

Would the stitching adversely affect the current capacity of the traces and defeat the objective? Or would it allow for better heat management and thus actually increase the current capacity?

Or would it have no effect whatsoever?

And what of the effect of 50/60Hz through the two traces with FR4 dielectric between them? Would doubling, with or without stitching, have an effect?

  • \$\begingroup\$ You might want to double check your title, and say why you think the voltage applied might affect the answer. \$\endgroup\$
    – The Photon
    Oct 23, 2016 at 16:49
  • \$\begingroup\$ Should say 5A not 5V \$\endgroup\$
    – Majenko
    Oct 23, 2016 at 16:51
  • \$\begingroup\$ I mention the voltage as it's mains. So AC, so wondering if the two traces with dielectric between would be an issue and if stitching would have any good or bad effects. \$\endgroup\$
    – Majenko
    Oct 23, 2016 at 16:53

1 Answer 1


Stitching (with vias I assume) will increase your cost. According to PCB trace calculator, for a 1oz copper and 5A load you need a trace about 3mm wide (for 10C warming over ambient). Can you afford this? If not, the standard trick is to beef up the trace with solder build-up, as manufactures do in millions of PC power supplies.

Stitching, however, will slightly improve thermal management of the trace, since vias will increase the heat exchange between two traces in cases of bad board orientation relative to gravity direction, when one side has a depressed air convection relative to the other side.

  • \$\begingroup\$ The calculator I use says 2.77 for 1", which I already have (I have 3mm actually). This is more for over-current contingency planning, thermal management, and physical damage mitigation. I am particularly interested in if I do stitch and one trace gets broken if the remaining trace will cope with the current over the break point, and if there would be any other adverse effects. I am expecting 0.3mm vias, so ~10% of the trace width. Also any effects of two in-phase equal amplitude signals with 1.6mm FR4 dielectric between them that stitching would help with. \$\endgroup\$
    – Majenko
    Oct 23, 2016 at 17:33
  • \$\begingroup\$ I am also considering, if I do stitch, what the best pattern would be. I am leaning towards stitching the two edges of the traces in a zig-zag pattern (say 100 mil intervals on one side, and 100 mil + 50 mil offset on the other) so no two vias are opposite each other on the trace. \$\endgroup\$
    – Majenko
    Oct 23, 2016 at 17:39
  • 2
    \$\begingroup\$ @Ali Chen: forget solder build-up. Sn has a specific resistance 6 times higher than copper, Pb 12 times higher. Alloys are worse. You have to embed a copper wire into the solder to get any effect. Just increase trace width or use 70µm Cu base material instead of standard 35µm. \$\endgroup\$
    – Janka
    Oct 23, 2016 at 17:42
  • \$\begingroup\$ @Janka, yes, solder alloy has higher resistivity than copper, but the build-up can be 0.5mm or more on a 1mm trace, which more than compensates for the lack of conductivity, so the trace current carrying capacity increases by 100-150%. As I said, millions and millions of PC PS use this technique, with apparent success. I can't forget about this, every time I open up a PS, it reminds me. :-) \$\endgroup\$ Oct 23, 2016 at 18:05
  • 1
    \$\begingroup\$ Sorry, I made a mistake. The assumed 0.5mm solder build-up over 1mm-wide trace will provide additional conductor with 1.84x conductivity of a 35um 1mm wide copper trace. Acting in parallel, this build-up will improve the DC carrying capability of such trace by a factor of 2.8. Nearly three times. \$\endgroup\$ Oct 23, 2016 at 21:59

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