Basically I need to find out if there is a feature that allows one to enter stimulus into an FPGA without using things like signal generators. Altera FPGAs have a feature implemented via Quartus called signal tap II. This allows requird signals to be tapped, stored in internal memory and then streamed via JTAG into Altera Quartus II and viewed on screen. This is similar to how one would use a logic analyzer. So, the idea is like this:
Is there a way to have "signal tap in reverse" i.e I provide a simulus that is stored in memory blocks in design and not part of actual design, as soon as the FPGA goes into user mode it shall read from these memory blocks (it contains all signals including reset) and uses the standard system clock that also goes into the memory blocks. The stimulus is read out when the end of stimulus is reached, the reset signal is asserted again and the stimlus reading starts over again and this continues in endless loop, or could be setup to run only once after configuration.
Does such a feature exist?