I am quite a novice in VHDL, but I decided to practice today my skills on designing a full adder. Simple task I thought, except that I somehow cannot manage to simulate my code correctly, even though when I compile it I dont get an error.
The error states only Fatal Error [file location of test bench] line 21, but whatever I try, I am not able to get rid of that error. If I force values through the command line to simulate my full adder without the test bench, the simulation gives me 'U' signals when I actually mentioned it to be '0'. So I am confused and totally lost; hoping somebody smart out there who can help me.
Here the code of the full adder:
library IEEE; use IEEE.std_logic_1164.all; entity full_adder is port(a,b,c_in: in std_logic; sum, carry: out std_logic); end full_adder; architecture SumAndCarry of full_adder is signal s1, s2, s3: std_logic; constant gate_delay: time:= 5 ns; begin L1: s1 <= a xor b after gate_delay; L2: s3 <= a and b after gate_delay; L3: sum <= s1 xor c_in after gate_delay; L4: s2 <= s1 and c_in after gate_delay; L5: carry <= s2 or s3 after gate_delay; end SumAndCarry;
And here the test bench I have prepared to test it:
library IEEE; use IEEE.std_logic_1164.all; entity FullAdder_tb is end FullAdder_tb; architecture testbench of FullAdder_tb is component full_adder is port(a,b,c_in: in std_logic;--You simply replace bit with std_logic sum, carry: out std_logic); end component; signal at, bt, ct, sumt, carryt: std_logic; begin at <= '0' after 50 ns, '1' after 100 ns, '0' after 50 ns; bt <= '0' after 50 ns, '1' after 50 ns, '0' after 50 ns, '1' after 50 ns;--This is line 21! ct <= '0' after 200 ns; Lbl1: Full_Adder port map (a => at, b=>bt, c_in=>ct, sum=>sumt, carry=>carryt); end testbench;
Hope everything is clear...