0
\$\begingroup\$

I am quite a novice in VHDL, but I decided to practice today my skills on designing a full adder. Simple task I thought, except that I somehow cannot manage to simulate my code correctly, even though when I compile it I dont get an error.

The error states only Fatal Error [file location of test bench] line 21, but whatever I try, I am not able to get rid of that error. If I force values through the command line to simulate my full adder without the test bench, the simulation gives me 'U' signals when I actually mentioned it to be '0'. So I am confused and totally lost; hoping somebody smart out there who can help me.

Here the code of the full adder:

 library IEEE;
 use IEEE.std_logic_1164.all; 

 entity full_adder is
 port(a,b,c_in: in std_logic;
 sum, carry: out std_logic);
 end full_adder;

 architecture SumAndCarry of full_adder is

 signal s1, s2, s3: std_logic;
 constant gate_delay: time:= 5 ns;
 begin 

 L1: s1 <= a xor b after gate_delay;
 L2: s3 <= a and b after gate_delay;
 L3: sum <= s1 xor c_in after gate_delay;
 L4: s2 <= s1 and c_in after gate_delay;
 L5: carry <= s2 or s3 after gate_delay;

 end SumAndCarry;

And here the test bench I have prepared to test it:

 library IEEE;
 use IEEE.std_logic_1164.all; 

 entity FullAdder_tb is
 end FullAdder_tb;


 architecture testbench of FullAdder_tb is
 component full_adder is
 port(a,b,c_in: in std_logic;--You simply replace bit with std_logic
     sum, carry: out std_logic);
 end component;
 signal at, bt, ct, sumt, carryt: std_logic;
 begin
 at <= '0' after 50 ns,
     '1' after 100 ns,
     '0' after 50 ns;
 bt <= '0' after 50 ns,
     '1' after 50 ns,
     '0' after 50 ns,
     '1' after 50 ns;--This is line 21!
 ct <= '0' after 200 ns;
 Lbl1: Full_Adder port map (a => at, b=>bt, c_in=>ct, sum=>sumt, carry=>carryt);
 end testbench;

Hope everything is clear...

\$\endgroup\$
3
  • \$\begingroup\$ You haven't indicated which line in the testbench is line 21. These particular errors are detectable at analysis (compile) time. I'm surprised Modelsim produces run time errors. \$\endgroup\$ – user8352 Oct 25 '16 at 4:31
  • \$\begingroup\$ ghdl (0.34dev) produces very clear error messages at compile time for all the errors here, I'd be very surprised if Modelsim doesn't. \$\endgroup\$ – user_1818839 Oct 25 '16 at 9:23
  • \$\begingroup\$ As I said, the code is fine. No compile errors, even in other programs such as quartus prime. I found though the mistake, the time steps I take should be in increasing order. (I thought these statements work in sequence.) \$\endgroup\$ – user3604362 Oct 25 '16 at 10:00
0
\$\begingroup\$

There are errors in your signal assignment waveforms signals at and bt in the testbench.

From IEEE Std 1076-2008 10.5.2.2 Executing a simple assignment statement para 6 (excerpted):

... Thus, the evaluation of a waveform results in a sequence of transactions, where each transaction corresponds to one waveform element in the waveform. These transactions are called new transactions. It is an error if the sequence of new transactions is not in ascending order with respect to time.

The new transactions are appended to the projected output waveform and measured from the current time.

Fixing the scheduled time of future transactions on at and bt in the testbench:

library IEEE;
use IEEE.std_logic_1164.all; 

entity full_adder is
port(a,b,c_in: in std_logic;
sum, carry: out std_logic);
end full_adder;

architecture SumAndCarry of full_adder is

signal s1, s2, s3: std_logic;
constant gate_delay: time:= 5 ns;
begin 

L1: s1 <= a xor b after gate_delay;
L2: s3 <= a and b after gate_delay;
L3: sum <= s1 xor c_in after gate_delay;
L4: s2 <= s1 and c_in after gate_delay;
L5: carry <= s2 or s3 after gate_delay;

end SumAndCarry;

library ieee;
use ieee.std_logic_1164.all; -- ADDED MISSING CONTEXT CLAUSE

entity FullAdder_tb is
end FullAdder_tb;

architecture testbench of FullAdder_tb is
component full_adder is
port(a,b,c_in: in std_logic;--You simply replace bit with std_logic
    sum, carry: out std_logic);
end component;
signal at, bt, ct, sumt, carryt: std_logic;
begin
at <= '0' after 50 ns,
    '1' after 100 ns,
    '0' after 150 ns;  -- WAS 50 ns
bt <= '0' after 50 ns,
    '1' after 100 ns,  -- WAS 50 ns
    '0' after 150 ns,  -- WAS 50 ns
    '1' after 200 ns;  -- WAS 50 ns
ct <= '0' after 200 ns;
Lbl1: Full_Adder port map (a => at, b=>bt, c_in=>ct, sum=>sumt, carry=>carryt);
end testbench;

(Also note the context clause added to full_adder).

Gives:

fulladder_tb.png

Note the long delay before assigning ct is causing the 'U' on sumt. It would be useful to initialize ct.

\$\endgroup\$
1
  • \$\begingroup\$ Ah! Thank you~ That solved my problem! It actually makes sense now that I think about it. And yeah, for ct, the 200 can be changed to 0 ns... Awesome! Thanks a lot! \$\endgroup\$ – user3604362 Oct 25 '16 at 10:04
0
\$\begingroup\$

With modelsim you need to make sure your are compiling all the files, and that your simulating the correct module. In this case you need to make sure that your testbench is the 'toplevel' module being simulated.

You need to eliminate all errors before you can reliably run your simulation. I'm not positive, because usually I keep most of my wires the same name, but I think you have your port map wires backwards. Since you haven't posted the error (you should always post the error) I can't tell you what is going on.

You may want to go out and do a few vhdl tutorials to learn how modelsim works before you start rolling your own stuff. There are many others if you google.

\$\endgroup\$
2
  • \$\begingroup\$ The error is mentioned. As I said, when I compile the codes, I have no errors. Yet when I simulate it, all my signals are set to 'U' and the test bench is unable to run. \$\endgroup\$ – user3604362 Oct 24 '16 at 23:19
  • \$\begingroup\$ The funny thing is, this is also from a tutorial, literally copied. The only new thing is the test bench, but even if I directly simulate the full adder using the command line, I still get the 'U' signals. \$\endgroup\$ – user3604362 Oct 24 '16 at 23:22

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.