# Do you use VHDL nowadays?

I'm an Electrical Engineering student and I'm studying the hardware description language known as VHDL. I searched for it on Google looking for an IDE (I'm on a mac), but this language seems pretty dead.

So here is my question: in my future job as an electrical engineer will VHDL be useful to me? Are you using it?

UPDATE: Thank you everyone for the answers, I was clearly wrong with my first impression.

• What makes you think VHDL is dead? – Kellenjb Feb 13 '12 at 15:26
• I'm coming from a programming background and maybe I have a distorted vision of the reality, trying to compare two different fields. – Francesco Feb 13 '12 at 15:34
• I use VHDL with Altera and Xilinx FPGAs. It's supported by the Altera Quartus II and Xilinx ISE IDEs, as is Verilog. VHDL and Verilog seem to be roughly equal in popularity. – Leon Heller Feb 13 '12 at 15:54
• @Francesco Did you consider IDEs for other operating systems? From what I hear and see (but I could be wrong) in general there is a distinct lack of electrical engineering software in general for Macintosh. – AndrejaKo Feb 13 '12 at 16:08
• To Leon's comment, here's a question about VHDL vs Verilog: electronics.stackexchange.com/questions/16767/vhdl-or-verilog – Kellenjb Feb 13 '12 at 16:16

I use ONLY VHDL. It is far from dead. A couple of years ago it seemed like a 50/50 split between people using VHDL or Verilog (anecdotal evidence at best), but I doubt that it has changed much since then.

The most recent version of VHDL is "VHDL-2008", which in language standard terms was just yesterday.

• About three years ago a market report by Gary Smith EDA indicated a 50/50 split, with a faster growth for (System)Verilog. – Philippe Feb 21 '12 at 18:12

If you plan on working with programmable logic (e.g. FPGAs, not MCUs), VHDL and Verilog are the two languages you'll have to know. As a student, you'll probably have to learn both, use both and be examined in both. That was certainly the case for me (and I only took a few courses in ASIC design), though it was a long time ago.

Chances are either VHDL or Verilog will be preferable to you. I have a personal preference for Verilog, but knowing both helps.

As a future engineer, you can roughly double the chances of getting a good job in designing with FPGAs (and similar technologies) if you can use both Verilog and VHDL.

You should try to make the choice as irrelevant (to you) as you can, personal preferences aside. A language is just a means of attaining a goal, not an end in itself. Consider yourself lucky there are only two big HDLs out there. If you were a computer scientist, you'd have to learn a good dozen entirely different families of programming languages, and be able to learn a new one in hours, and understand its idiom in days.

Aside: programming languages (used to control the operation of Turing Machines) and hardware description languages (used to control the configuration of hardware) are different things altogether, although most HDLs have structures that either make them look like programming languages, or make them programming languages also. If this is confusing, just accept that you can't write a computer operating system in VHDL, same as you can't describe a RISC CPU in C.

VHDL is very much not a dead language. Your problem is that you were searching for tools to do VHDL programming on Mac OS X. Unfortunately, there are very few options for doing decent HDL (Verilog or VHDL) programming from a Mac. The only real option I know of (where real is quite a flexible adjective) is the Icarus Verilog Simulator.

The other real option, and the one I choose, is to Boot Camp your Mac and pick up Windows or Linux based tools that way.

Yes, I use VHDL on a daily basis. And C++, C, Matlab, Python. Less frequently I also use TCL, Perl, Makefiles, Bash-scripts, and even CMD scripts (aagh!)

VHDL is definately not dead. It competes with the language Verilog (or more accurately, with Verilog's Sucessor, SystemVerilog).

My understanding is that for whatever reason historically VHDL was the more common language for FPGA design, and the reverse for ASIC design.

The languages are syntaticly rather different, but semenatically similar enough that for design purposes they are almost interchangable. As such it mostly depends on the organization as to which is used.

Now compared to programming languages (VHDL and Verilog are HDLs (Hardware Description Langauges), not programming languages) there are not many worthwhile free tools. The best tools are generally expensive commerical products (although they often offer free academic licenses).

I used to use VHDL because it was what I was taught in school. I now use Verilog simply because it the only language that most open source FPGA/HDL tools support such as YOSYS, IceStorm, PrjTrellis etc. I have a Mac so I have to use open source FPGA programmers and compilers as neither Xilinx, Altera, nor Lattice release their tools for OS X. One could use Wine, but I've discovered the open source tools to be orders of magnitude faster(not to mention they're free).

Lastly, the biggest rationale I have for using verilog is the tool Verilator. Verilator allows you to compile verilog into C code and literally instantiate hardware on your computer that can communicate with other libraries. I do Convolutional Network design in HDL, so this means I can have python push data to my virtual FPGA and receive an image back. I've even heard of crazy stuff where the creator of ZipCPU loaded and interacted with data streams on his virtual FPGA. Verilator unfortunately only supports verilog - but it is what it is.

All that aside, my Embedded systems professor said that VHDL was historically popular for education and government use because it was an open standard from the start. After remaining closed for 10 or so years, verilog was finally published as an open standard. By this time, VHDL had already left its mark.

I will echo the other answers in saying VHDL is far from dead. It is one of two languages you may choose from to design an FPGA from. As stated in other answers, Verilog is your only other choice. Thusfar I have only worked in places that use VHDL (it seems to be regional, which language will be used). If you want tools to design in either, I would suggest picking up either Xilinx's XST suite or Altera's Quartus suite.

If you wish to get a good gauge on whether VHDL is alive, try searching some job-hunting sites like dice.com, monster.com, or indeed.com for vhdl. You'll find its a little more of a niche that standard C/C++ programming, but very desirable.

I've used VHDL at Intel and Qualcomm, as well as at various defense industry companies and at startups.

Qualcomm's MSM chips that go in cell phones are written in VHDL. I agree with the other posters that it seems to be regional, though.

Electrical engineering is a wide field and you may end up not ever needing Vhdl for example if you decide to specialize in RF. But if you are going into Digital Hardware and/or Fpga design then you are going to need either VHDL or Verilog and a bunch of other scripting languages like TCL, Perl, Python and Matlab. There isn't a need to be too concerned with the choice between VHDL and Verilog. They are just a language to express your design. The fundamentals of digital design remain the same.

As others have said, VHDL and Verilog are used to describe digital hardware design. The code is then processed by a "synthesis" tool that generates the logic which shall achieve our described hardware which basically results in a netlist.

VHDL is more popular in Europe and Verilog is more popular in USA. However, it is best to learn both of them. In a give job you will mostly only use one of them. However, may have to read code in either.

I have been an engineer for a few years and have seen VHDL being used in all cases. I am from the UK.

The primary point of contention is that since designs have become so much complex over the years, we need new approach in design verification. This is where we use simulation to prove that our design works as intended. This is the most critical stage of design cycle and the one where most time is spent.

Many years ago, a language called SystemVerilog was created to add powerful features into Verilog which can then be used to improve design its design verification capabilities. SystemVerilog contains Verilog within it, and more. SystemVerilog is a HVL i.e hardware verification language, while Verilog and VHDL are HDL i.e Hardware description language. This made VHDL look weaker han Verilog since if one wants to use a single language and software to write complex designs and verify them using complex techniques like constrained random stimulus generation and assertion based testbenches, they would have to opt for SystemVerilog and drop VHDL. However, more recently a methodology called OSVVM has been created that takes advantage of VHDL-2008 to achieve same features found in SystemVerilog but in VHDL. I am not exactly sure how close the OSVVM methodology of VHDL comes to the UVM methodology of SystemVerilog.

At this time, you could learn either and be safe.

I have to say VHDL is dying. reasons:

1. vhdl2008 is not fully supported by EDA yet. It is 2018 now
2. Libraries are just ok. But if you want fancy features, it is too hard. For example, there are too many questions about ieee_proposed on the internet. File IO is crazy.
3. I like the strict style, but it should not be inconvenient or redundant. v2008 makes it better, but it is not fully supported by EDA yet. So, I still use v93.
4. SystemVerilog domains verification.

I know there are some companies that have put SV to a higher priority than VHDL regarding RTL design. So for the beginner, just learn SV.

VHDL is the devil's language. All of commercial industry and west coast military use Verilog. Only the old dinosaurs military companies on the east coast (like BAE) use VHDL. It's about a 50% reduction in typing when using Verilog verse VHDL. Now you are starting to see east coast military firms finally break down and adopt Verilog. Have you ever heard of System VHDL, no? VHDL will eventually go by the wayside like the software language Ada.

• What about the rest of the world ;-) – user8352 Jul 23 '14 at 23:55
• You forgot about the OSVVM methodology which makes it possible for VHDL to match SystemVerilog. – quantum231 Dec 30 '18 at 0:16
• There seems to be little need for "System VHDL" as vanilla VHDL already has many of the features SystemVerilog tries to tack onto vanilla Verilog. Also, the type safety is nice. – Richard the Spacecat Aug 28 '19 at 8:37