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I am creating a homebrew CPU. My current design has a TTL 'AND' gate that takes two inputs. The CLK (running at 1Mhz) and another that determines if the CLK should propagate onwards to update a register.

This all seems reasonable but I would like to remove the TTL chip from the design as I only need it for this one 'AND' gate. I found that two diodes can be used to create an AND gate in the following way...

enter image description here

Is this a safe thing to do with a 1Mhz CLK input? Will it provide as reliable an output as a traditional TTL 'AND' gate?

EDIT:

The CPU is made up of 74HC series TTL chips. With 5v being a logical 1 and 0v being a logic 0. With a clock speed of 1Mhz and. Input 'A' is the clock line and input 'B' is a control line coming from the instruction decode logic. It will have been stable for several 100ns before the next clock tick.

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  • \$\begingroup\$ Related: electronics.stackexchange.com/questions/172968/… \$\endgroup\$ – dim Oct 25 '16 at 9:37
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    \$\begingroup\$ If that was your only AND gate, what is the rest of the CPU made with? \$\endgroup\$ – Dave Tweed Oct 25 '16 at 9:48
  • \$\begingroup\$ Check the wikipedia article on DTL \$\endgroup\$ – PlasmaHH Oct 25 '16 at 9:49
  • \$\begingroup\$ @DaveTweed possibly Babbage gear train logic? \$\endgroup\$ – Ian Bland Oct 25 '16 at 10:12
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    \$\begingroup\$ Note that "what is the rest of the CPU made with?" is a serious question. You've told us nothing about what might be driving the inputs of your proposed circuit, nor about the load(s) this circuit is expected to drive. Furthermore, you've told us nothing about the circuit itself -- what are the values for V and the resistor? In general, what are the voltage levels that your CPU considers to be "low" and "high"? How much timing margin do you have on the clock period? \$\endgroup\$ – Dave Tweed Oct 25 '16 at 10:24
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Yes, should work in your limited situation...where inputs are driven from HCMOS logic. This "diode AND" gate's output should drive a HCMOS input. An additional limitation would not allow two or more of these gates in series, without a HCMOS buffer between them.
Noise immunity is compromised by this gate, because a logic low at the output does not fall close to zero volts, but hovers one diode-drop higher. If you use common silicon diodes (1N914), the diode adds about 0.64v to the logic zero. If your HCMOS logic runs with a low supply voltage like 3v, then the logic threshold voltage might be around 1.5v, leaving you with about a volt for noise immunity. A HCMOS AND gate has better noise immunity.
Current consumption of this AND gate is high, and dependent on logic state, compared with an equivalent HCMOS AND gate. To make this gate fast-acting, the pull-up resistor must be small (1K ohm or less). If either input is logic "low", current draw from the Vdd supply, through the driving gate to ground is large. This single gate may draw more current than your entire CPU. Be aware that this pull-up resistor must go to the same Vdd supply that powers the rest of your HCMOS CPU.
Diode speed shouldn't be a problem. Schottky diodes would be preferable, with high-speed silicon diodes a second choice. Even Germanium point-contact diodes could be used.

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  • \$\begingroup\$ Any thoughts about the advantages of two diodes and a resistor, vs. using a diode to one signal and a resistor to the other? \$\endgroup\$ – supercat Oct 25 '16 at 15:03
  • \$\begingroup\$ @supercat, Could do the simpler D & R. Noise immunity for 3 of 4 logic state inputs improves. Current consumption is high for only 1 of 4 logic state inputs (an improvement from 3-of-4). The series resistor-input is slower than the diode-input. \$\endgroup\$ – glen_geek Oct 25 '16 at 16:20
  • \$\begingroup\$ A falling edge on the series-resistor input while the other input would be high, but a rising edge should be the same. I was thinking of using the resistor+diode circuit in a project I'm building to gate the TPB pulse with A14 on an COSMAC-1802 design. TPB is high once every 8 input clocks, so a resistor to TPB and a diode to A14 should only burn power about 1/8 of the time. The CPU clock is 1.8Mhz, so the resistor trick should be fast enough. \$\endgroup\$ – supercat Oct 25 '16 at 17:44
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This may actually work, assuming that the voltage drop over diode plus the voltage of the "logical zero" in the inputs A and B is still clearly less than the threshold voltage of the output.

Also the resistor must be selected so that maximal allowed current through the outputs connected to A, B and diodes remains in range.

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  • \$\begingroup\$ And the resistor must also be small enough that it can reach the needed rise time against the capacitance of the following logic inputs. \$\endgroup\$ – JRE Oct 25 '16 at 13:37
  • \$\begingroup\$ This is also correct. \$\endgroup\$ – h22 Oct 25 '16 at 14:21

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